On 6/3/2020 12:20 PM, Jim Quinlan wrote:
> From: Jim Quinlan <jquin...@broadcom.com>
> 
> Older BrcmSTB chips do not have a separate register for MSI interrupts; the
> MSIs are in a register that also contains unrelated interrupts.  In
> addition, the interrupts lie in bits [31..24] for these legacy chips.  This
> commit provides common code for both legacy and non-legacy MSI interrupt
> registers.
> 
> Signed-off-by: Jim Quinlan <jquin...@broadcom.com>

Acked-by: Florian Fainelli <f.faine...@gmail.com>
-- 
Florian

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