Hi Sivaprakash,
Sivaprakash Murugesan <sivap...@codeaurora.org> wrote on Fri, 12 Jun
2020 12:19:49 +0530:
> BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
> is set by writing BAM_MODE_EN bit on NAND_CTRL register.
>
> NAND_CTRL is an operational register and in BAM mode operational
> registers are read only.
>
> So, before writing into NAND_CTRL register check if BAM mode is already
So, before enabling BAM mode by writing the NAND_CTRL register, check
if BAM mode was already enabled by the bootloader.
> enabled by bootloader, and set BAM mode only if it is not set already.
>
> Signed-off-by: Sivaprakash Murugesan <sivap...@codeaurora.org>
> ---
> [V3]
> * Changed commit message to give a small info about BAM
> drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> b/drivers/mtd/nand/raw/qcom_nandc.c
> index e0c55bb..4827edd 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct
> qcom_nand_controller *nandc)
> /* enable ADM or BAM DMA */
> if (nandc->props->is_bam) {
> nand_ctrl = nandc_read(nandc, NAND_CTRL);
> - nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> + /* NAND_CTRL is an operational registers, and CPU
> + * access to operational registers are read only
> + * in BAM mode. So update the NAND_CTRL register
> + * only if it is not in BAM mode. In most cases BAM
BAM mode already (Bootloaders
might have already entered
this mode).
> + * mode will be enabled in bootloader
> + */
> + if (!(nand_ctrl | BAM_MODE_EN))
> + nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> } else {
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> }
Thanks,
Miquèl
