We should clear DBM bit of all PTEs and flush TLB, then sync dirty log, which promise we won't miss any dirty status set by hardware.
Signed-off-by: Keqian Zhu <[email protected]> --- arch/arm64/kvm/arm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 92f0b40a30fa..76cab4c0b5a6 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -93,6 +93,12 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, r = -EINVAL; } else { r = 0; + if (kvm->arch.hw_dirty_log && !cap->args[0]) { + mutex_lock(&kvm->slots_lock); + kvm_mmu_clear_dbm_all(kvm); + kvm_mmu_sync_dirty_log_all(kvm); + mutex_unlock(&kvm->slots_lock); + } kvm->arch.hw_dirty_log = cap->args[0]; } break; -- 2.19.1
