On Tue, Jun 16, 2020 at 1:20 AM Sean Christopherson
<sean.j.christopher...@intel.com> wrote:
>
> On Tue, Jun 16, 2020 at 03:33:07PM +0800, Xiaoyao Li wrote:
> > Only MSR address range 0x800 through 0x8ff is architecturally reserved
> > and dedicated for accessing APIC registers in x2APIC mode.
> >
> > Fixes: 0105d1a52640 ("KVM: x2apic interface to lapic")
> > Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
> > ---
>
> And perhaps more importantly, there are real MSRs that are overlapped,
> e.g. MSR_IA32_TME_ACTIVATE. This probably warrants a Cc to stable; as you
> found out the hard way, this breaks ignore_msrs.
>
> Reviewed-by: Sean Christopherson <sean.j.christopher...@intel.com>
Excellent find!
Reviewed-by: Jim Mattson <jmatt...@google.com>
