tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 69119673bd50b176ded34032fadd41530fb5af21 commit: 07842d54b95a1c236ba2bc237e32eeac476fc967 drm/amd/display: add Renoir to kconfig date: 10 months ago config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): git checkout 07842d54b95a1c236ba2bc237e32eeac476fc967 # save the attached .config to linux build tree make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <l...@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:55:6:
warning: no previous prototype for 'rn_update_clocks' [-Wmissing-prototypes]
55 | void rn_update_clocks(struct clk_mgr *clk_mgr_base,
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c: In
function 'rn_dump_clk_registers':
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:199:37:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
199 | if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass
> 4)
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:202:37:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
202 | if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass
> 4)
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:205:38:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
205 | if (regs_and_bypass->dispclk_bypass < 0 ||
regs_and_bypass->dispclk_bypass > 4)
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:208:39:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
208 | if (regs_and_bypass->dprefclk_bypass < 0 ||
regs_and_bypass->dprefclk_bypass > 4)
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c: At top
level:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:315:6:
warning: no previous prototype for 'rn_get_clk_states' [-Wmissing-prototypes]
315 | void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:325:6:
warning: no previous prototype for 'rn_enable_pme_wa' [-Wmissing-prototypes]
325 | void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:408:6:
warning: no previous prototype for 'build_watermark_ranges'
[-Wmissing-prototypes]
408 | void build_watermark_ranges(struct clk_bw_params *bw_params, struct
pp_smu_wm_range_sets *ranges)
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:465:6:
>> warning: no previous prototype for 'clk_mgr_helper_populate_bw_params'
>> [-Wmissing-prototypes]
465 | void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params,
struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:43:
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:221:29: warning:
'UVD0_BASE' defined but not used [-Wunused-const-variable=]
221 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00,
0x02403000, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:214:29: warning:
'USB0_BASE' defined but not used [-Wunused-const-variable=]
214 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0,
0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:207:29: warning:
'UMC_BASE' defined but not used [-Wunused-const-variable=]
207 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:200:29: warning:
'THM_BASE' defined but not used [-Wunused-const-variable=]
200 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:193:29: warning:
'SMUIO_BASE' defined but not used [-Wunused-const-variable=]
193 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00,
0x02401000, 0x00440000, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:186:29: warning:
'SDMA0_BASE' defined but not used [-Wunused-const-variable=]
186 | static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:179:29: warning:
'PCIE0_BASE' defined but not used [-Wunused-const-variable=]
179 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:172:29: warning:
'OSSSYS_BASE' defined but not used [-Wunused-const-variable=]
172 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000,
0, 0, 0 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:165:29: warning:
'NBIF0_BASE' defined but not used [-Wunused-const-variable=]
165 | static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014,
0x00000D20, 0x00010400, 0x0241B000 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:158:29: warning:
'MP1_BASE' defined but not used [-Wunused-const-variable=]
158 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400,
0x00E80000, 0x00EC0000, 0x00F00000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:151:29: warning:
'MP0_BASE' defined but not used [-Wunused-const-variable=]
151 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00,
0x00DC0000, 0x00E00000, 0x00E40000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:144:29: warning:
'MMHUB_BASE' defined but not used [-Wunused-const-variable=]
144 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:137:29: warning:
'L2IMU0_BASE' defined but not used [-Wunused-const-variable=]
137 | static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000,
0x00900000, 0x04FC0000, 0x055C0000 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:130:29: warning:
'ISP_BASE' defined but not used [-Wunused-const-variable=]
130 | static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:123:29: warning:
'IOHC0_BASE' defined but not used [-Wunused-const-variable=]
123 | static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000,
0x04EC0000, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:116:29: warning:
'HDP_BASE' defined but not used [-Wunused-const-variable=]
116 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:109:29: warning:
'HDA_BASE' defined but not used [-Wunused-const-variable=]
109 | static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:102:29: warning:
'GC_BASE' defined but not used [-Wunused-const-variable=]
102 | static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000,
0x02402C00, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:95:29: warning:
'FUSE_BASE' defined but not used [-Wunused-const-variable=]
95 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0,
0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:88:29: warning:
'DPCS_BASE' defined but not used [-Wunused-const-variable=]
88 | static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0,
0x000034C0, 0x00009000, 0x02403C00 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:81:29: warning:
'DMU_BASE' defined but not used [-Wunused-const-variable=]
81 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0,
0x000034C0, 0x00009000, 0x02403C00 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:74:29: warning:
'DIO_BASE' defined but not used [-Wunused-const-variable=]
74 | static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:67:29: warning:
'DF_BASE' defined but not used [-Wunused-const-variable=]
67 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0,
0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:60:29: warning:
'DBGU_IO0_BASE' defined but not used [-Wunused-const-variable=]
60 | static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400,
0, 0, 0 } },
| ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:46:29: warning:
'ATHUB_BASE' defined but not used [-Wunused-const-variable=]
46 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0,
0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:39:29: warning:
'ACP_BASE' defined but not used [-Wunused-const-variable=]
39 | static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0,
0, 0 } },
| ^~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32,
from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/resource.h:28,
from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/hw/clk_mgr_internal.h:36,
from drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:27:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:122:22:
warning: 'DP_DVI_CONVERTER_ID_4' defined but not used [-Wunused-const-variable=]
122 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
| ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:120:22:
warning: 'DP_VGA_LVDS_CONVERTER_ID_3' defined but not used
[-Wunused-const-variable=]
120 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:118:22:
warning: 'DP_VGA_LVDS_CONVERTER_ID_2' defined but not used
[-Wunused-const-variable=]
118 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:29,
from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/hw/dccg.h:29,
from drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c:26:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning:
'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
| ^~~~~~~~~~~~~~~~~~
--
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:288:14: note:
in expansion of macro 'BASE'
288 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) +
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:165:2: note: in
expansion of macro 'SRI'
165 | SRI(CURSOR_CONTROL, CURSOR0_, id), | ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:598:2: note: in
expansion of macro 'TF_REG_LIST_DCN20'
598 | TF_REG_LIST_DCN20(id), | ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:604:2: note: in
expansion of macro 'tf_regs'
604 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:484:52: note: (near
initialization for 'tf_regs[2].CURSOR_CONTROL')
484 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:279:25: note:
in expansion of macro 'DMU_BASE__INST0_SEG2'
279 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:288:14: note:
in expansion of macro 'BASE'
288 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) +
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:165:2: note: in
expansion of macro 'SRI'
165 | SRI(CURSOR_CONTROL, CURSOR0_, id), | ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:598:2: note: in
expansion of macro 'TF_REG_LIST_DCN20'
598 | TF_REG_LIST_DCN20(id), | ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:604:2: note: in
expansion of macro 'tf_regs'
604 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:484:52: warning:
initialized field overwritten [-Woverride-init]
484 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:279:25: note:
in expansion of macro 'DMU_BASE__INST0_SEG2'
279 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:288:14: note:
in expansion of macro 'BASE'
288 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) +
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:165:2: note: in
expansion of macro 'SRI'
165 | SRI(CURSOR_CONTROL, CURSOR0_, id), | ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:598:2: note: in
expansion of macro 'TF_REG_LIST_DCN20'
598 | TF_REG_LIST_DCN20(id), | ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:605:2: note: in
expansion of macro 'tf_regs'
605 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:484:52: note: (near
initialization for 'tf_regs[3].CURSOR_CONTROL')
484 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:279:25: note:
in expansion of macro 'DMU_BASE__INST0_SEG2'
279 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:288:14: note:
in expansion of macro 'BASE'
288 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) +
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:165:2: note: in
expansion of macro 'SRI'
165 | SRI(CURSOR_CONTROL, CURSOR0_, id), | ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:598:2: note: in
expansion of macro 'TF_REG_LIST_DCN20'
598 | TF_REG_LIST_DCN20(id), | ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:605:2: note: in
expansion of macro 'tf_regs'
605 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:707:20:
warning: no previous prototype for 'dcn21_i2c_hw_create' [-Wmissing-prototypes]
707 | struct dce_i2c_hw *dcn21_i2c_hw_create(
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:975:6: warning:
no previous prototype for 'dcn21_calculate_wm' [-Wmissing-prototypes]
975 | void dcn21_calculate_wm(
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1058:6:
warning: no previous prototype for 'dcn21_validate_bandwidth'
[-Wmissing-prototypes]
1058 | bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1188:32:
warning: no previous prototype for 'dcn21_opp_create' [-Wmissing-prototypes]
1188 | struct output_pixel_processor *dcn21_opp_create(
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1204:26:
warning: no previous prototype for 'dcn21_timing_generator_create'
[-Wmissing-prototypes]
1204 | struct timing_generator *dcn21_timing_generator_create(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1226:13:
warning: no previous prototype for 'dcn21_mpc_create' [-Wmissing-prototypes]
1226 | struct mpc *dcn21_mpc_create(struct dc_context *ctx)
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1254:35:
warning: no previous prototype for 'dcn21_dsc_create' [-Wmissing-prototypes]
1254 | struct display_stream_compressor *dcn21_dsc_create(
| ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1318:20:
>> warning: no previous prototype for 'dummy_set_wm_ranges'
>> [-Wmissing-prototypes]
1318 | enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
| ^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1324:20:
>> warning: no previous prototype for 'dummy_get_dpm_clock_table'
>> [-Wmissing-prototypes]
1324 | enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1331:22:
>> warning: no previous prototype for 'dcn21_pp_smu_create'
>> [-Wmissing-prototypes]
1331 | struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
| ^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1343:6:
>> warning: no previous prototype for 'dcn21_pp_smu_destroy'
>> [-Wmissing-prototypes]
1343 | void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1362:24:
warning: no previous prototype for 'dcn21_stream_encoder_create'
[-Wmissing-prototypes]
1362 | struct stream_encoder *dcn21_stream_encoder_create(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:62:
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:484:52: warning:
initialized field overwritten [-Woverride-init]
484 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:279:25: note:
in expansion of macro 'DMU_BASE__INST0_SEG2'
279 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:284:15: note:
in expansion of macro 'BASE'
284 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + |
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:157:2: note: in
expansion of macro 'SR'
157 | SR(DCFCLK_CNTL), | ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:283:2: note: in
expansion of macro 'HWSEQ_DCN_REG_LIST'
283 | HWSEQ_DCN_REG_LIST(), | ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1380:3: note:
in expansion of macro 'HWSEQ_DCN21_REG_LIST'
1380 | HWSEQ_DCN21_REG_LIST()
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:484:52: note: (near
initialization for 'hwseq_reg.DCFCLK_CNTL')
484 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:279:25: note:
in expansion of macro 'DMU_BASE__INST0_SEG2'
279 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:281:19: note:
in expansion of macro 'BASE_INNER'
281 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:284:15: note:
in expansion of macro 'BASE'
284 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + |
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:157:2: note: in
expansion of macro 'SR'
157 | SR(DCFCLK_CNTL), | ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:283:2: note: in
expansion of macro 'HWSEQ_DCN_REG_LIST'
283 | HWSEQ_DCN_REG_LIST(), | ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1380:3: note:
in expansion of macro 'HWSEQ_DCN21_REG_LIST'
1380 | HWSEQ_DCN21_REG_LIST()
| ^~~~~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:73:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.h:274:23: warning:
'abm_gain_stepsize' defined but not used [-Wunused-const-variable=]
274 | static const uint32_t abm_gain_stepsize = 0x0060;
| ^~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:62:
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:221:29: warning:
'UVD0_BASE' defined but not used [-Wunused-const-variable=]
221 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00,
0x02403000, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:214:29: warning:
'USB0_BASE' defined but not used [-Wunused-const-variable=]
214 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0,
0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:207:29: warning:
'UMC_BASE' defined but not used [-Wunused-const-variable=]
207 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:200:29: warning:
'THM_BASE' defined but not used [-Wunused-const-variable=]
200 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:193:29: warning:
'SMUIO_BASE' defined but not used [-Wunused-const-variable=]
193 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00,
0x02401000, 0x00440000, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:186:29: warning:
'SDMA0_BASE' defined but not used [-Wunused-const-variable=]
186 | static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:179:29: warning:
'PCIE0_BASE' defined but not used [-Wunused-const-variable=]
179 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:172:29: warning:
'OSSSYS_BASE' defined but not used [-Wunused-const-variable=]
172 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000,
0, 0, 0 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:165:29: warning:
'NBIF0_BASE' defined but not used [-Wunused-const-variable=]
165 | static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014,
0x00000D20, 0x00010400, 0x0241B000 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:158:29: warning:
'MP1_BASE' defined but not used [-Wunused-const-variable=]
158 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400,
0x00E80000, 0x00EC0000, 0x00F00000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:151:29: warning:
'MP0_BASE' defined but not used [-Wunused-const-variable=]
151 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00,
0x00DC0000, 0x00E00000, 0x00E40000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:144:29: warning:
'MMHUB_BASE' defined but not used [-Wunused-const-variable=]
144 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800,
0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:137:29: warning:
'L2IMU0_BASE' defined but not used [-Wunused-const-variable=]
137 | static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000,
0x00900000, 0x04FC0000, 0x055C0000 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:130:29: warning:
'ISP_BASE' defined but not used [-Wunused-const-variable=]
130 | static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0,
0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:123:29: warning:
'IOHC0_BASE' defined but not used [-Wunused-const-variable=]
123 | static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000,
0x04EC0000, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:116:29: warning:
'HDP_BASE' defined but not used [-Wunused-const-variable=]
116 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0,
0, 0 } },
vim +/clk_mgr_helper_populate_bw_params +465
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 464
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 @465 void
clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct
dpm_clocks *clock_table, struct hw_asic_id *asic_id)
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 466 {
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 467 int i;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 468
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 469
ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 470
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 471 for (i = 0; i <
PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 472 if
(clock_table->FClocks[i].Freq == 0)
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 473 break;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 474
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 475
bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 476
bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 477
bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 478
bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 479
bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 480 }
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 481
bw_params->clk_table.num_entries = i;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 482
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 483 bw_params->vram_type =
asic_id->vram_type;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 484 bw_params->num_channels
= asic_id->vram_width / DDR4_DRAM_WIDTH;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 485
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 486 for (i = 0; i <
WM_SET_COUNT; i++) {
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 487
bw_params->wm_table.entries[i].wm_inst = i;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 488
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 489 if
(clock_table->FClocks[i].Freq == 0) {
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 490
bw_params->wm_table.entries[i].valid = false;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 491
continue;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 492 }
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 493
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 494
bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 495
bw_params->wm_table.entries[i].valid = true;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 496 }
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 497
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 498 if
(bw_params->vram_type == LpDdr4MemType) {
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 499 /*
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 500 * WM set D
will be re-purposed for memory retraining
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 501 */
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 502
bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 503
bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 504
bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 505
bw_params->wm_table.entries[WM_D].valid = true;
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 506 }
4edb6fc9187860 Bhawanpreet Lakha 2019-07-26 507
:::::: The code at line 465 was first introduced by commit
:::::: 4edb6fc91878603f325c79314ee7675558932f7f drm/amd/display: Add Renoir
clock manager
:::::: TO: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
:::::: CC: Alex Deucher <alexander.deuc...@amd.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
