Add compatible string, update the clock table,
add fsl,asrc-rate and fsl,asrc-width property.
Signed-off-by: Shengjiu Wang <shengjiu.w...@nxp.com>
---
arch/arm/boot/dts/imx6sx.dtsi | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 94e3df47d1ad..7d4856ffd239 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -390,18 +390,28 @@
};
asrc: asrc@2034000 {
+ compatible = "fsl,imx6sx-asrc",
"fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50
IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
- <&clks IMX6SX_CLK_ASRC_IPG>,
- <&clks IMX6SX_CLK_SPDIF>,
- <&clks IMX6SX_CLK_SPBA>;
- clock-names = "mem", "ipg", "asrck",
"spba";
- dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
- <&sdma 19 20 1>, <&sdma 20 20 1>,
- <&sdma 21 20 1>, <&sdma 22 20 1>;
+ clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
+ <&clks IMX6SX_CLK_ASRC_MEM>,
<&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks
0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks
0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks
0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPDIF>,
<&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2",
"asrck_3", "asrck_4",
+ "asrck_5", "asrck_6",
"asrck_7", "asrck_8",
+ "asrck_9", "asrck_a",
"asrck_b", "asrck_c",
+ "asrck_d", "asrck_e",
"asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
+ <&sdma 19 23 1>, <&sdma 20 23 1>,
+ <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
status = "okay";
};
};
--
2.21.0
