Hi Borislav, On Sun, 21 Jun 2020 12:53:50 +0200 Borislav Petkov <[email protected]> wrote: > > + acme for an FYI. > > On Sun, Jun 21, 2020 at 04:33:23PM +1000, Stephen Rothwell wrote: > > Hi all, > > > > After merging the tip tree, today's linux-next build (perf) failed > > like this: > > > > In file included from trace/beauty/tracepoints/x86_msr.c:10: > > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: > > initialized field overwritten [-Werror=override-init] > > 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC", > > | ^~~~~~~~~~~ > > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near > > initialization for 'x86_AMD_V_KVM_MSRs[640]') > > > > Caused by commit > > > > 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs") > > > > I have used the tip tree from next-20200618 for tooday. > > Thanks, I saw that once but then got distracted to something of higher > prio. :-\ > > I'll apply this after testing it a bit: > > --- > From: Borislav Petkov <[email protected]> > Date: Sun, 21 Jun 2020 12:41:53 +0200 > Subject: [PATCH] x86/msr: Move the F15h MSRs where they belong > > 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs") > > moved the three F15h power MSRs to the architectural list but that was > wrong as they belong in the family 0x15 list. That also caused: > > In file included from trace/beauty/tracepoints/x86_msr.c:10: > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: > initialized field overwritten [-Werror=override-init] > 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC", > | ^~~~~~~~~~~ > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near > initialization for 'x86_AMD_V_KVM_MSRs[640]') > > due to MSR_F15H_PTSC ending up being defined twice. Move them where they > belong and drop the duplicate. > > While at it, update the msr-index.h copy to pick up the changes from > > 7e5b3c267d25 ("x86/speculation: Add Special Register Buffer Data Sampling > (SRBDS) mitigation") > > Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs") > Reported-by: Stephen Rothwell <[email protected]> > Signed-off-by: Borislav Petkov <[email protected]> > --- > arch/x86/include/asm/msr-index.h | 5 ++--- > tools/arch/x86/include/asm/msr-index.h | 9 ++++++--- > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/arch/x86/include/asm/msr-index.h > b/arch/x86/include/asm/msr-index.h > index eb9537254920..63ed8fe35738 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -422,11 +422,8 @@ > #define MSR_AMD_PERF_CTL 0xc0010062 > #define MSR_AMD_PERF_STATUS 0xc0010063 > #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 > -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a > -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b > #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 > #define MSR_AMD64_OSVW_STATUS 0xc0010141 > -#define MSR_F15H_PTSC 0xc0010280 > #define MSR_AMD_PPIN_CTL 0xc00102f0 > #define MSR_AMD_PPIN 0xc00102f1 > #define MSR_AMD64_CPUID_FN_1 0xc0011004 > @@ -469,6 +466,8 @@ > #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 > > /* Fam 15h MSRs */ > +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a > +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b > #define MSR_F15H_PERF_CTL 0xc0010200 > #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL > #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) > diff --git a/tools/arch/x86/include/asm/msr-index.h > b/tools/arch/x86/include/asm/msr-index.h > index 7dfd45bb6cdb..63ed8fe35738 100644 > --- a/tools/arch/x86/include/asm/msr-index.h > +++ b/tools/arch/x86/include/asm/msr-index.h > @@ -128,6 +128,10 @@ > #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ > #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ > > +/* SRBDS support */ > +#define MSR_IA32_MCU_OPT_CTRL 0x00000123 > +#define RNGDS_MITG_DIS BIT(0) > + > #define MSR_IA32_SYSENTER_CS 0x00000174 > #define MSR_IA32_SYSENTER_ESP 0x00000175 > #define MSR_IA32_SYSENTER_EIP 0x00000176 > @@ -418,11 +422,8 @@ > #define MSR_AMD_PERF_CTL 0xc0010062 > #define MSR_AMD_PERF_STATUS 0xc0010063 > #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 > -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a > -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b > #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 > #define MSR_AMD64_OSVW_STATUS 0xc0010141 > -#define MSR_F15H_PTSC 0xc0010280 > #define MSR_AMD_PPIN_CTL 0xc00102f0 > #define MSR_AMD_PPIN 0xc00102f1 > #define MSR_AMD64_CPUID_FN_1 0xc0011004 > @@ -465,6 +466,8 @@ > #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 > > /* Fam 15h MSRs */ > +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a > +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b > #define MSR_F15H_PERF_CTL 0xc0010200 > #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL > #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
I applied that patch to the tip tree merge today. Tested-by: Stephen Rothwell <[email protected]> # build tested -- Cheers, Stephen Rothwell
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