On 20/06/2020 18:14, Martin Blumenstingl wrote:
> Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
> know the relation between this clock and RGMII Ethernet. It turns out
> that fclk_div2 is used as "timing adjustment clock" to generate the RX
> delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
> using the RX delay on the PHY side or not using a RX delay at all then
> this clock can be disabled.
>
> Signed-off-by: Martin Blumenstingl <martin.blumensti...@googlemail.com>
> ---
> drivers/clk/meson/meson8b.c | 7 -------
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index edc09d050ecf..3d826711c820 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = {
> &meson8b_fclk_div2_div.hw
> },
> .num_parents = 1,
> - /*
> - * FIXME: Ethernet with a RGMII PHYs is not working if
> - * fclk_div2 is disabled. it is currently unclear why this
> - * is. keep it enabled until the Ethernet driver knows how
> - * to manage this clock.
> - */
> - .flags = CLK_IS_CRITICAL,
> },
> };
>
>
Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
