On Friday, June 12, 2020 8:09:57 PM CEST Srinivas Pandruvada wrote:
> Add additional bit for OOB (Out of band) enabling of P-states. In this
> case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of the
> MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" as
> OOB condition.
>
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com>
> ---
> v2
> - As suggested by Doug add OOB in debug message
> - Atleast added local definition of OOB mask
>
> drivers/cpufreq/intel_pstate.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
> index 8e23a698ce04..4e9bfd2509b8 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -2677,6 +2677,7 @@ static struct acpi_platform_list plat_info[] __initdata
> = {
> { } /* End */
> };
>
> +#define BITMASK_OOB (BIT(8) | BIT(18))
> static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
> {
> const struct x86_cpu_id *id;
> @@ -2686,8 +2687,9 @@ static bool __init
> intel_pstate_platform_pwr_mgmt_exists(void)
> id = x86_match_cpu(intel_pstate_cpu_oob_ids);
> if (id) {
> rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
> - if (misc_pwr & (1 << 8)) {
> - pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
> + if (misc_pwr & BITMASK_OOB) {
> + pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
> + pr_debug("P states are controlled in Out of Band mode
> by the firmware/hardware\n");
> return true;
> }
> }
>
Applied as 5.8-rc material with some edits in the subject/changelog, thanks!
