From: Alex Deucher <alexander.deuc...@amd.com>

commit b7f839d292948142eaab77cedd031aad0bfec872 upstream.

We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation.  Check both to determine
the proper blanked state.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane 
state")
Cc: nicholas.kazlaus...@amd.com
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>

---
 drivers/gpu/drm/amd/display/dc/core/dc.c |   24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1011,9 +1011,17 @@ static void program_timing_sync(
                        }
                }
 
-               /* set first pipe with plane as master */
+               /* set first unblanked pipe as master */
                for (j = 0; j < group_size; j++) {
-                       if (pipe_set[j]->plane_state) {
+                       bool is_blanked;
+
+                       if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
+                               is_blanked =
+                                       
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
+                       else
+                               is_blanked =
+                                       
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
+                       if (!is_blanked) {
                                if (j == 0)
                                        break;
 
@@ -1034,9 +1042,17 @@ static void program_timing_sync(
                                status->timing_sync_info.master = false;
 
                }
-               /* remove any other pipes with plane as they have already been 
synced */
+               /* remove any other unblanked pipes as they have already been 
synced */
                for (j = j + 1; j < group_size; j++) {
-                       if (pipe_set[j]->plane_state) {
+                       bool is_blanked;
+
+                       if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
+                               is_blanked =
+                                       
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
+                       else
+                               is_blanked =
+                                       
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
+                       if (!is_blanked) {
                                group_size--;
                                pipe_set[j] = pipe_set[group_size];
                                j--;


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