Mike Kravetz <mike.krav...@oracle.com> writes: > On 6/24/20 2:26 AM, Bibo Mao wrote: >> When set_pmd_at is called in function do_huge_pmd_anonymous_page, >> new tlb entry can be added by software on MIPS platform. >> >> Here add update_mmu_cache_pmd when pmd entry is set, and >> update_mmu_cache_pmd is defined as empty excepts arc/mips platform. >> This patch has no negative effect on other platforms except arc/mips >> system. > > I am confused by this comment. It appears that update_mmu_cache_pmd > is defined as non-empty on arc, mips, powerpc and sparc architectures. > Am I missing something? > > If those architectures do provide update_mmu_cache_pmd, then the previous > patch and this one now call update_mmu_cache_pmd with the actual faulting > address instead of the huge page aligned address. This was intentional > for mips. However, are there any potential issues on the other architectures? > I am no expert in any of those architectures. arc looks like it could be > problematic as update_mmu_cache_pmd calls update_mmu_cache and then > operates on (address & PAGE_MASK). That could now be different. >
Also we added update_mmu_cache_pmd to update a THP entry. That could be different from a hugetlb entry on some architectures. If we need to do hugetlb equivalent for update_mmu_cache, we should add a different function. -aneesh
