Add the PMU so we can get proper perf event support on this SoC.

Signed-off-by: Konrad Dybcio <konradyb...@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi 
b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index e8b801813f14..c4c9a108ae1e 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -130,6 +130,11 @@ memory {
                reg = <0 0 0 0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| 
IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
-- 
2.27.0

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