[PATCH v5 9/9] clocksource/drivers/timer-atmel-tcb: add sama5d2 support

[Alexandre Belloni]

The first divisor for the sama5d2 is actually the gclk selector. Because
the currently remaining divisors are fitting the use case, currently ensure
it is skipped.

Signed-off-by: Alexandre Belloni <alexandre.bell...@bootlin.com>
---
 drivers/clocksource/timer-atmel-tcb.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-atmel-tcb.c 
b/drivers/clocksource/timer-atmel-tcb.c
index ccb77b9cb489..e373b02d509a 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -359,9 +359,15 @@ static struct atmel_tcb_config tcb_sam9x5_config = {
        .counter_width = 32,
 };
 
+static struct atmel_tcb_config tcb_sama5d2_config = {
+       .counter_width = 32,
+       .has_gclk = 1,
+};
+
 static const struct of_device_id atmel_tcb_of_match[] = {
        { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
        { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
+       { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
        { /* sentinel */ }
 };
 
@@ -426,7 +432,10 @@ static int __init tcb_clksrc_init(struct device_node *node)
 
        /* How fast will we be counting?  Pick something over 5 MHz.  */
        rate = (u32) clk_get_rate(t0_clk);
-       for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
+       i = 0;
+       if (tc.tcb_config->has_gclk)
+               i = 1;
+       for (; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
                unsigned divisor = atmel_tcb_divisors[i];
                unsigned tmp;
 
-- 
2.26.2