Hello Alexander, On 06/07/2020 08:27, Alexander A. Klimov wrote: > Rationale: > Reduces attack surface on kernel devs opening the links for MITM > as HTTPS traffic is much harder to manipulate. > > Deterministic algorithm: > For each file: > If not .svg: > For each line: > If doesn't contain `\bxmlns\b`: > For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: > If both the HTTP and HTTPS versions > return 200 OK and serve the same content: > Replace HTTP with HTTPS. > > Signed-off-by: Alexander A. Klimov <grandmas...@al2klimov.de>
Acked-by: Alexander Sverdlin <alexander.sverd...@gmail.com> > --- > Continuing my work started at 93431e0607e5. > > If there are any URLs to be removed completely or at least not HTTPSified: > Just clearly say so and I'll *undo my change*. > See also https://lkml.org/lkml/2020/6/27/64 > > If there are any valid, but yet not changed URLs: > See https://lkml.org/lkml/2020/6/26/837 > > arch/arm/mach-ep93xx/clock.c | 2 +- > arch/arm/mach-ep93xx/soc.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c > index 2810eb5b2aca..48efefbb54f8 100644 > --- a/arch/arm/mach-ep93xx/clock.c > +++ b/arch/arm/mach-ep93xx/clock.c > @@ -571,7 +571,7 @@ static int __init ep93xx_clock_init(void) > /* > * EP93xx SSP clock rate was doubled in version E2. For more information > * see: > - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf > + * https://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf > */ > if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) > clk_spi.rate /= 2; > diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h > index f2dace1c9154..9e4a3b245434 100644 > --- a/arch/arm/mach-ep93xx/soc.h > +++ b/arch/arm/mach-ep93xx/soc.h > @@ -28,7 +28,7 @@ > * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design > * Guidelines" for more information. This document can be found at: > * > - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf > + * https://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf > */ > > #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */