On Mon, Jun 29, 2020 at 07:21:29PM +0800, Tony W Wang-oc wrote: > Add new Zhaoxin CPU features for enumeration in /proc/cpuinfo: > SM2, SM2_EN, SM3, SM4, SM3_EN, SM4_EN, PARALLAX, PARALLAX_EN, > TM3, TM3_EN, RNG2, RNG2_EN, PHE2, PHE2_EN, RSA, RSA_EN. > > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 0] SM2 > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 1] SM2_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 4] SM3 SM4 > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 5] SM3_EN SM4_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 16] PARALLAX > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 17] PARALLAX_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 20] TM3 > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 21] TM3_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 22] RNG2 > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 23] RNG2_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 25] PHE2 > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 26] PHE2_EN > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 27] RSA > CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 28] RSA_EN > > SM2, SM3, SM4 are Chinese Cipher Security algorithm. > PARALLAX is a feature that automatically adjusts processors's voltage > as a function of temperature. > TM3 is Zhaoxin CPU Thermal Monitor v3. > RNG2 is Zhaoxin Random Number Generation v2. > PHE2 is Zhaoxin Padlock Hash Engine v2. > RSA is Zhaoxin hardware support for RSA algorithm.
Boris is on vacation, so I'll ask the question that he would ask if he were here ... "Are there some follow-up patches that use all of these feature bits?" Just adding bits to /proc/cpuinfo is of limited use. -Tony
