From: Bolarinwa Olayemi Saheed <[email protected]> On failure pcie_capability_read_dword() sets it's last parameter, val to 0. In which case (val & PCI_EXP_DEVCTL2_LTR_EN) evaluates to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x).
This bug can be avoided without changing the function's behaviour if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_word() to ensure success. Suggested-by: Bjorn Helgaas <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Bolarinwa Olayemi Saheed <[email protected]> --- drivers/misc/cardreader/rts5227.c | 5 +++-- drivers/misc/cardreader/rts5249.c | 5 +++-- drivers/misc/cardreader/rts5260.c | 5 +++-- drivers/misc/cardreader/rts5261.c | 5 +++-- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/misc/cardreader/rts5227.c b/drivers/misc/cardreader/rts5227.c index 3a9467aaa435..7a20a4898d07 100644 --- a/drivers/misc/cardreader/rts5227.c +++ b/drivers/misc/cardreader/rts5227.c @@ -92,6 +92,7 @@ static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) { u16 cap; + int ret; rtsx_pci_init_cmd(pcr); @@ -105,8 +106,8 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) /* LED shine disabled, set initial shine cycle period */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); /* Configure LTR */ - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap); - if (cap & PCI_EXP_DEVCTL2_LTR_EN) + ret = pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap); + if (!ret && (cap & PCI_EXP_DEVCTL2_LTR_EN)) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3); /* Configure OBFF */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03); diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c index 6c6c9e95a29f..2b05e8663431 100644 --- a/drivers/misc/cardreader/rts5249.c +++ b/drivers/misc/cardreader/rts5249.c @@ -95,6 +95,7 @@ static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &(pcr->option); u32 lval; + int ret; if (CHK_PCI_PID(pcr, PID_524A)) rtsx_pci_read_config_dword(pcr, @@ -118,8 +119,8 @@ static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) if (option->ltr_en) { u16 val; - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); + if (!ret && (val & PCI_EXP_DEVCTL2_LTR_EN)) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c index 7a9dbb778e84..934aeaeebfaf 100644 --- a/drivers/misc/cardreader/rts5260.c +++ b/drivers/misc/cardreader/rts5260.c @@ -498,6 +498,7 @@ static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &pcr->option; u32 lval; + int ret; rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval); @@ -518,8 +519,8 @@ static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) if (option->ltr_en) { u16 val; - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); + if (!ret && (val & PCI_EXP_DEVCTL2_LTR_EN)) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c index 195822ec858e..2b6f61696e19 100644 --- a/drivers/misc/cardreader/rts5261.c +++ b/drivers/misc/cardreader/rts5261.c @@ -438,9 +438,10 @@ static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); if (option->ltr_en) { u16 val; + int ret; - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); - if (val & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); + if (!ret && (val & PCI_EXP_DEVCTL2_LTR_EN)) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); -- 2.18.2
