Set the corresponding advertised and supported link modes according
to the detected transceiver type and device capabilities.
Signed-off-by: Alexander Lobakin <aloba...@marvell.com>
Signed-off-by: Igor Russkikh <irussk...@marvell.com>
---
drivers/net/ethernet/qlogic/qed/qed_hsi.h | 4 +
drivers/net/ethernet/qlogic/qed/qed_main.c | 112 ++++++++++++++++-----
drivers/net/ethernet/qlogic/qed/qed_mcp.c | 9 +-
3 files changed, 98 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
index 0d0a109d94b4..ebc25b34e491 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
@@ -12027,6 +12027,10 @@ struct public_port {
#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37
+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38
+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39
+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a
u32 wol_info;
u32 wol_pkt_len;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_main.c
b/drivers/net/ethernet/qlogic/qed/qed_main.c
index 8a0b8da19547..9df27c3f5cab 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_main.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_main.c
@@ -1695,21 +1695,38 @@ static void qed_fill_link_capability(struct qed_hwfn
*hwfn,
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
__set_bit(QED_LM_20000baseKR2_Full, if_caps);
- /* For DAC media multiple speed capabilities are supported*/
- capability = capability & speed_mask;
+ /* For DAC media multiple speed capabilities are supported */
+ capability |= speed_mask;
+
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
__set_bit(QED_LM_1000baseKX_Full, if_caps);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
__set_bit(QED_LM_10000baseCR_Full, if_caps);
+
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
- __set_bit(QED_LM_40000baseCR4_Full, if_caps);
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_40G_CR4:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
+ __set_bit(QED_LM_40000baseCR4_Full, if_caps);
+ default:
+ break;
+ }
+
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
__set_bit(QED_LM_25000baseCR_Full, if_caps);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
__set_bit(QED_LM_50000baseCR2_Full, if_caps);
+
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
- __set_bit(QED_LM_100000baseCR4_Full, if_caps);
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_100G_CR4:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
+ __set_bit(QED_LM_100000baseCR4_Full, if_caps);
+ default:
+ break;
+ }
break;
case MEDIA_BASE_T:
@@ -1727,10 +1744,15 @@ static void qed_fill_link_capability(struct qed_hwfn
*hwfn,
if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
__set_bit(QED_LM_FIBRE, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_1000BASET:
__set_bit(QED_LM_1000baseT_Full, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
+ break;
+ case ETH_TRANSCEIVER_TYPE_10G_BASET:
__set_bit(QED_LM_10000baseT_Full, if_caps);
+ default:
+ break;
+ }
}
break;
@@ -1739,47 +1761,85 @@ static void qed_fill_link_capability(struct qed_hwfn
*hwfn,
case MEDIA_XFP_FIBER:
case MEDIA_MODULE_FIBER:
__set_bit(QED_LM_FIBRE, if_caps);
+ capability |= speed_mask;
- if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
- if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
- (tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX))
+ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_1G_LX:
+ case ETH_TRANSCEIVER_TYPE_1G_SX:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
__set_bit(QED_LM_1000baseKX_Full, if_caps);
- }
+ default:
+ break;
+ }
- if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR)
+ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_10G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
__set_bit(QED_LM_10000baseSR_Full, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR)
+ break;
+ case ETH_TRANSCEIVER_TYPE_10G_LR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
__set_bit(QED_LM_10000baseLR_Full, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM)
+ break;
+ case ETH_TRANSCEIVER_TYPE_10G_LRM:
__set_bit(QED_LM_10000baseLRM_Full, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER)
+ break;
+ case ETH_TRANSCEIVER_TYPE_10G_ER:
__set_bit(QED_LM_10000baseR_FEC, if_caps);
- }
+ default:
+ break;
+ }
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
__set_bit(QED_LM_20000baseKR2_Full, if_caps);
- if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) {
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR)
+ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_25G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
__set_bit(QED_LM_25000baseSR_Full, if_caps);
- }
+ default:
+ break;
+ }
- if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) {
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4)
+ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_40G_LR4:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
__set_bit(QED_LM_40000baseLR4_Full, if_caps);
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4)
+ break;
+ case ETH_TRANSCEIVER_TYPE_40G_SR4:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
__set_bit(QED_LM_40000baseSR4_Full, if_caps);
- }
+ default:
+ break;
+ }
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
__set_bit(QED_LM_50000baseKR2_Full, if_caps);
if (capability &
- NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) {
- if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4)
+ NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
+ switch (tcvr_type) {
+ case ETH_TRANSCEIVER_TYPE_100G_SR4:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
__set_bit(QED_LM_100000baseSR4_Full, if_caps);
- }
+ break;
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
+ __set_bit(QED_LM_100000baseLR4_ER4_Full,
+ if_caps);
+ default:
+ break;
+ }
break;
case MEDIA_KR:
diff --git a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
index 2d12bb27560c..b10a92488630 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
@@ -2193,6 +2193,11 @@ int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn,
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
break;
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR:
+ *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
+ NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
+ break;
case ETH_TRANSCEIVER_TYPE_40G_CR4:
case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
@@ -2223,8 +2228,10 @@ int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn,
*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
break;
case ETH_TRANSCEIVER_TYPE_10G_BASET:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
+ case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
*p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
- NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
+ NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
break;
default:
DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n",
--
2.25.1
