[PATCH 5.7 143/244] clk: qcom: gcc: Add GPU and NPU clocks for SM8150

[Greg Kroah-Hartman]

From: Vinod Koul <vk...@kernel.org>

commit f73a4230d5bbc8fc7e1a2479ac997f786111c7bb upstream.

Add the GPU and NPU clocks for SM8150. They were missed in earlier
addition of clock driver.

Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for 
SM8150")
Signed-off-by: Vinod Koul <vk...@kernel.org>
Link: https://lkml.kernel.org/r/20200513065420.32735-1-vk...@kernel.org
Signed-off-by: Stephen Boyd <sb...@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>

---
 drivers/clk/qcom/gcc-sm8150.c |   64 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -1616,6 +1616,36 @@ static struct clk_branch gcc_gpu_cfg_ahb
        },
 };
 
+static struct clk_branch gcc_gpu_gpll0_clk_src = {
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(15),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_gpll0_clk_src",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &gpll0.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(16),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_gpll0_div_clk_src",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &gcc_gpu_gpll0_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_gpu_iref_clk = {
        .halt_reg = 0x8c010,
        .halt_check = BRANCH_HALT,
@@ -1698,6 +1728,36 @@ static struct clk_branch gcc_npu_cfg_ahb
        },
 };
 
+static struct clk_branch gcc_npu_gpll0_clk_src = {
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(18),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_npu_gpll0_clk_src",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &gpll0.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_npu_gpll0_div_clk_src = {
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(19),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_npu_gpll0_div_clk_src",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &gcc_npu_gpll0_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_npu_trig_clk = {
        .halt_reg = 0x4d00c,
        .halt_check = BRANCH_VOTED,
@@ -3374,12 +3434,16 @@ static struct clk_regmap *gcc_sm8150_clo
        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
        [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
        [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+       [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
+       [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
        [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
        [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
        [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
        [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
        [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
        [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
+       [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
+       [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
        [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
        [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
        [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,