On Monday, October 29, 2007 1:15 am Dave Airlie wrote: > Hi, > > We've uncovered a need when using the new memory manager to flush the > chipset global write buffers on certain intel chipset due to a lack > of coherency.. > > The attached patches add a new AGP interface for this purpose and > implements this in the Intel AGP driver. This stuff is based of some > guesswork in the 915 case from comments in the documentation :).
In this case, we're performing basically a dma_sync*(...DMA_TO_DEVICE) right? Can we be sure that a single flush is sufficient? Is there any window between when we flush and when we start accessing memory with the device that we could get into more caching trouble? > Unfortuantely the 965 BIOS doesn't set this stuff up properly and it > doesn't use a standard BAR address, so I have to do it by hand, I'd > appreciate any commentary particularly in the setting up of the > resource stuff. Looks reasonable, I'm not sure we can do much better. The only concern I have is that allocating some more PCI space like that may end up clobbering some *other* hidden BIOS mapping, but there's not a whole lot we can do about that. Jesse - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
