On Thu, Jul 9, 2020 at 9:07 PM qianjun <qianjun.ker...@gmail.com> wrote: > > From: qianjun <qian...@didiglobal.com> > > Use L1Miss to replace L1Hit to describe the correct scene > > Signed-off-by: qianjun <qian...@didiglobal.com> > --- > tools/perf/Documentation/perf-c2c.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/Documentation/perf-c2c.txt > b/tools/perf/Documentation/perf-c2c.txt > index 98efdab..083e99a 100644 > --- a/tools/perf/Documentation/perf-c2c.txt > +++ b/tools/perf/Documentation/perf-c2c.txt > @@ -186,7 +186,7 @@ For each cacheline in the 1) list we display following > data: > Store Reference - Total, L1Hit, L1Miss > Total - all store accesses > L1Hit - store accesses that hit L1 > - L1Hit - store accesses that missed L1 > + L1Miss - store accesses that missed L1 > > Load Dram > - count of local and remote DRAM accesses > -- > 1.8.3.1 >
hi man I think it's a problem :)
