Hi,
On Sat, Aug 1, 2020 at 11:14 AM Taniya Das <t...@codeaurora.org> wrote:
>
> Update the clock controller nodes for Low power audio subsystem
> functionality.
>
> Signed-off-by: Taniya Das <t...@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index d46b383..7cf8bfe 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,videocc-sc7180.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> @@ -3312,6 +3313,30 @@
> qcom,msa-fixed-perm;
> status = "disabled";
> };
> +
> + lpasscc: clock-controller@62d00000 {
> + compatible = "qcom,sc7180-lpasscorecc";
> + reg = <0 0x62d00000 0 0x50000>,
> + <0 0x62780000 0 0x30000>;
> + reg-names = "lpass_core_cc", "lpass_audio_cc";
> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "bi_tcxo";
> + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + lpass_hm: clock-controller@63000000 {
> + compatible = "qcom,sc7180-lpasshm";
> + reg = <0 0x63000000 0 0x28>;
> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "bi_tcxo";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> };
You end up adding a blank line at the end that Bjron can probably fix
when applying, but other than that this looks good to me.
Reviewed-by: Douglas Anderson <diand...@chromium.org>
