From: Christoph Lameter <[EMAIL PROTECTED]> Date: Thu, 1 Nov 2007 15:11:41 -0700 (PDT)
> On Thu, 1 Nov 2007, David Miller wrote: > > > The remaining issue with accessing per-cpu areas at multiple virtual > > addresses is D-cache aliasing. > > But that is not an issue for physicallly mapped caches. Right but I'd like to use this on sparc64 which has L1 D-cache aliasing on some chips :-) - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
