[PATCH v17 08/12] soc: mediatek: Add extra sram control

[Weiyi Lu]

For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do
the extra sram isolation control or not.

Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
Reviewed-by: Nicolas Boichat <drink...@chromium.org>
---
 drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index ec62143..4587cef 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -26,6 +26,7 @@
 
 #define MTK_SCPD_ACTIVE_WAKEUP         BIT(0)
 #define MTK_SCPD_FWAIT_SRAM            BIT(1)
+#define MTK_SCPD_SRAM_ISO              BIT(2)
 #define MTK_SCPD_CAPS(_scpd, _x)       ((_scpd)->data->caps & (_x))
 
 #define SPM_VDE_PWR_CON                        0x0210
@@ -57,6 +58,8 @@
 #define PWR_ON_BIT                     BIT(2)
 #define PWR_ON_2ND_BIT                 BIT(3)
 #define PWR_CLK_DIS_BIT                        BIT(4)
+#define PWR_SRAM_CLKISO_BIT            BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT          BIT(6)
 
 #define PWR_STATUS_CONN                        BIT(1)
 #define PWR_STATUS_DISP                        BIT(3)
@@ -290,6 +293,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, 
void __iomem *ctl_addr)
                        return ret;
        }
 
+       if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO))     {
+               val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+               writel(val, ctl_addr);
+               udelay(1);
+               val &= ~PWR_SRAM_CLKISO_BIT;
+               writel(val, ctl_addr);
+       }
+
        return 0;
 }
 
@@ -299,8 +310,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, 
void __iomem *ctl_addr)
        u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
        int tmp;
 
-       val = readl(ctl_addr);
-       val |= scpd->data->sram_pdn_bits;
+       if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO))     {
+               val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
+               writel(val, ctl_addr);
+               val &= ~PWR_SRAM_ISOINT_B_BIT;
+               writel(val, ctl_addr);
+               udelay(1);
+       }
+
+       val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
        writel(val, ctl_addr);
 
        /* Either wait until SRAM_PDN_ACK all 1 or 0 */
-- 
1.8.1.1.dirty