-----Original Message----- From: Tom Rix <t...@redhat.com> Sent: Wednesday, August 5, 2020 7:02 PM To: Ardelean, Alexandru <alexandru.ardel...@analog.com>; linux-...@vger.kernel.org; linux-f...@vger.kernel.org; linux-kernel@vger.kernel.org Cc: mturque...@baylibre.com; sb...@kernel.org; m...@kernel.org; Caprioru, Mircea <mircea.capri...@analog.com> Subject: Re: [PATCH 5/6] include: fpga: adi-axi-common.h: add definitions for supported FPGAs
[External] On 8/4/20 4:06 AM, Alexandru Ardelean wrote: > From: Mircea Caprioru <mircea.capri...@analog.com> > > All (newer) FPGA IP cores supported by Analog Devices, store > information in the synthesized designs. This information describes > various parameters, including the family of boards on which this is > deployed, speed-grade, and so on. > > Currently, some of these definitions are deployed mostly on Xilinx > boards, but they have been considered also for FPGA boards from other vendors. > > The register definitions are described at this link: > https://wiki.analog.com/resources/fpga/docs/hdl/regmap > (the 'Base (common to all cores)' section). > > Signed-off-by: Mircea Caprioru <mircea.capri...@analog.com> > Signed-off-by: Alexandru Ardelean <alexandru.ardel...@analog.com> > --- > include/linux/fpga/adi-axi-common.h | 37 > +++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/include/linux/fpga/adi-axi-common.h > b/include/linux/fpga/adi-axi-common.h > index 141ac3f251e6..7cca2d62cc45 100644 > --- a/include/linux/fpga/adi-axi-common.h > +++ b/include/linux/fpga/adi-axi-common.h > @@ -13,6 +13,9 @@ > > #define ADI_AXI_REG_VERSION 0x0000 > > +#define ADI_AXI_REG_FPGA_INFO 0x001C > +#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140 > + > #define ADI_AXI_PCORE_VER(major, minor, patch) \ > (((major) << 16) | ((minor) << 8) | (patch)) > > @@ -20,4 +23,38 @@ > #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) > #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) > > +#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff) > + > +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) > +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) > +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) > + > +enum adi_axi_fgpa_technology { > enum types are defined but not used. It would be better to convert all of > these to #defines. > > These are only the Xilinx values. Need to add the Intel values from > https://urldefense.com/v3/__https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl__;!!A3Ni8CS0y2Y!tpLxcnpvcjFVEYz0mfRNW03dYet-iklk2s_eG4FmRmeyMOcldd8f-zpebB5NnJLOjl1rNw$ > > The #define names need to include XILINX or INTEL. Ah, good point. This patch was initially written before the Intel stuff was added. Will update. Apologies for the mis-formatted reply/email; will need to include my Gmail account to reply neater here. > Tom > + ADI_AXI_FPGA_TECH_UNKNOWN = 0, > + ADI_AXI_FPGA_TECH_SERIES7, > + ADI_AXI_FPGA_TECH_ULTRASCALE, > + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, > +}; > + > +enum adi_axi_fpga_family { > + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, > + ADI_AXI_FPGA_FAMILY_ARTIX, > + ADI_AXI_FPGA_FAMILY_KINTEX, > + ADI_AXI_FPGA_FAMILY_VIRTEX, > + ADI_AXI_FPGA_FAMILY_ZYNQ, > +}; > + > +enum adi_axi_fpga_speed_grade { > + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, > + ADI_AXI_FPGA_SPEED_1 = 10, > + ADI_AXI_FPGA_SPEED_1L = 11, > + ADI_AXI_FPGA_SPEED_1H = 12, > + ADI_AXI_FPGA_SPEED_1HV = 13, > + ADI_AXI_FPGA_SPEED_1LV = 14, > + ADI_AXI_FPGA_SPEED_2 = 20, > + ADI_AXI_FPGA_SPEED_2L = 21, > + ADI_AXI_FPGA_SPEED_2LV = 22, > + ADI_AXI_FPGA_SPEED_3 = 30, > +}; > + > #endif /* ADI_AXI_COMMON_H_ */
