For the operation type packet payload with load/store class, it misses to support below sub classes:
- A load/store targeting the general-purpose registers; - A load/store targeting unspecified registers; - An MRS or MSR operation at EL1 transformed to a load/store. This patch is to add support for these sub classes. Signed-off-by: Leo Yan <[email protected]> --- .../arm-spe-decoder/arm-spe-pkt-decoder.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index ab966885e892..095f344ee26c 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -395,6 +395,27 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, return ret; buf += ret; blen -= ret; + } else if ((payload & SPE_OP_PKT_LDST_SUBCLASS_MASK) == + SPE_OP_PKT_LDST_SUBCLASS_GP_REG) { + ret = snprintf(buf, buf_len, " GP-REG"); + if (ret < 0) + return ret; + buf += ret; + blen -= ret; + } else if ((payload & SPE_OP_PKT_LDST_SUBCLASS_MASK) == + SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG) { + ret = snprintf(buf, buf_len, " UNSPEC-REG"); + if (ret < 0) + return ret; + buf += ret; + blen -= ret; + } else if ((payload & SPE_OP_PKT_LDST_SUBCLASS_MASK) == + SPE_OP_PKT_LDST_SUBCLASS_MRS_MSR) { + ret = snprintf(buf, buf_len, " MRS-MSR"); + if (ret < 0) + return ret; + buf += ret; + blen -= ret; } return buf_len - blen; case SPE_OP_PKT_HDR_CLASS_BR_ERET: -- 2.17.1
