Hi Thomas, FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: fc3abb53250a90ba2150eebd182137c136f4d25a commit: 7505576d1c1ac0cfe85fdf90999433dd8b673012 MIPS: add support for SGI Octane (IP30) date: 10 months ago config: mips-randconfig-r022-20200903 (attached as .config) compiler: mips64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 7505576d1c1ac0cfe85fdf90999433dd8b673012 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> All errors (new ones prefixed by >>): mips64-linux-ld: arch/mips/kernel/signal.o: in function `restore_hw_fp_context': arch/mips/kernel/signal.c:141: undefined reference to `_restore_fp_context' mips64-linux-ld: arch/mips/kernel/signal.o: in function `save_hw_fp_context': arch/mips/kernel/signal.c:132: undefined reference to `_save_fp_context' mips64-linux-ld: arch/mips/kernel/traps.o: in function `trap_init': >> arch/mips/kernel/traps.c:2408: undefined reference to `handle_fpe' >> mips64-linux-ld: arch/mips/kernel/traps.c:2412: undefined reference to >> `handle_fpe' >> mips64-linux-ld: arch/mips/kernel/traps.c:2412: undefined reference to >> `handle_fpe' # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7505576d1c1ac0cfe85fdf90999433dd8b673012 git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 7505576d1c1ac0cfe85fdf90999433dd8b673012 vim +2408 arch/mips/kernel/traps.c 5b10496b6e6577f Atsushi Nemoto 2006-09-11 2267 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2268 void __init trap_init(void) ^1da177e4c3f415 Linus Torvalds 2005-04-16 2269 { 2a0b24f56c2492b Steven J. Hill 2013-03-25 2270 extern char except_vec3_generic; ^1da177e4c3f415 Linus Torvalds 2005-04-16 2271 extern char except_vec4; 2a0b24f56c2492b Steven J. Hill 2013-03-25 2272 extern char except_vec3_r4000; 172dcd935c34b02 Paul Burton 2019-04-30 2273 unsigned long i, vec_size; 172dcd935c34b02 Paul Burton 2019-04-30 2274 phys_addr_t ebase_pa; c65a5480ff29198 Atsushi Nemoto 2007-11-12 2275 c65a5480ff29198 Atsushi Nemoto 2007-11-12 2276 check_wait(); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2277 172dcd935c34b02 Paul Burton 2019-04-30 2278 if (!cpu_has_mips_r2_r6) { 172dcd935c34b02 Paul Burton 2019-04-30 2279 ebase = CAC_BASE; 172dcd935c34b02 Paul Burton 2019-04-30 2280 ebase_pa = virt_to_phys((void *)ebase); 172dcd935c34b02 Paul Burton 2019-04-30 2281 vec_size = 0x400; c195e079e9dd00f James Hogan 2016-09-01 2282 172dcd935c34b02 Paul Burton 2019-04-30 2283 memblock_reserve(ebase_pa, vec_size); 172dcd935c34b02 Paul Burton 2019-04-30 2284 } else { 172dcd935c34b02 Paul Burton 2019-04-30 2285 if (cpu_has_veic || cpu_has_vint) 172dcd935c34b02 Paul Burton 2019-04-30 2286 vec_size = 0x200 + VECTORSPACING*64; 172dcd935c34b02 Paul Burton 2019-04-30 2287 else 172dcd935c34b02 Paul Burton 2019-04-30 2288 vec_size = PAGE_SIZE; 172dcd935c34b02 Paul Burton 2019-04-30 2289 172dcd935c34b02 Paul Burton 2019-04-30 2290 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); f995adb0ac5bcfa Paul Burton 2019-04-30 2291 if (!ebase_pa) 8a7f97b902f4fb0 Mike Rapoport 2019-03-11 2292 panic("%s: Failed to allocate %lu bytes align=0x%x\n", 172dcd935c34b02 Paul Burton 2019-04-30 2293 __func__, vec_size, 1 << fls(vec_size)); c195e079e9dd00f James Hogan 2016-09-01 2294 c195e079e9dd00f James Hogan 2016-09-01 2295 /* c195e079e9dd00f James Hogan 2016-09-01 2296 * Try to ensure ebase resides in KSeg0 if possible. c195e079e9dd00f James Hogan 2016-09-01 2297 * c195e079e9dd00f James Hogan 2016-09-01 2298 * It shouldn't generally be in XKPhys on MIPS64 to avoid c195e079e9dd00f James Hogan 2016-09-01 2299 * hitting a poorly defined exception base for Cache Errors. c195e079e9dd00f James Hogan 2016-09-01 2300 * The allocation is likely to be in the low 512MB of physical, c195e079e9dd00f James Hogan 2016-09-01 2301 * in which case we should be able to convert to KSeg0. c195e079e9dd00f James Hogan 2016-09-01 2302 * c195e079e9dd00f James Hogan 2016-09-01 2303 * EVA is special though as it allows segments to be rearranged c195e079e9dd00f James Hogan 2016-09-01 2304 * and to become uncached during cache error handling. c195e079e9dd00f James Hogan 2016-09-01 2305 */ c195e079e9dd00f James Hogan 2016-09-01 2306 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) c195e079e9dd00f James Hogan 2016-09-01 2307 ebase = CKSEG0ADDR(ebase_pa); f995adb0ac5bcfa Paul Burton 2019-04-30 2308 else f995adb0ac5bcfa Paul Burton 2019-04-30 2309 ebase = (unsigned long)phys_to_virt(ebase_pa); 18022894eca1315 James Hogan 2016-09-01 2310 } e01402b115cccb6 Ralf Baechle 2005-07-14 2311 c6213c6c9c189ae Steven J. Hill 2013-06-05 2312 if (cpu_has_mmips) { c6213c6c9c189ae Steven J. Hill 2013-06-05 2313 unsigned int config3 = read_c0_config3(); c6213c6c9c189ae Steven J. Hill 2013-06-05 2314 c6213c6c9c189ae Steven J. Hill 2013-06-05 2315 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) c6213c6c9c189ae Steven J. Hill 2013-06-05 2316 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); c6213c6c9c189ae Steven J. Hill 2013-06-05 2317 else c6213c6c9c189ae Steven J. Hill 2013-06-05 2318 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); c6213c6c9c189ae Steven J. Hill 2013-06-05 2319 } c6213c6c9c189ae Steven J. Hill 2013-06-05 2320 6fb97effee5374a Kevin Cernekee 2011-11-16 2321 if (board_ebase_setup) 6fb97effee5374a Kevin Cernekee 2011-11-16 2322 board_ebase_setup(); 6650df3c380e0db David Daney 2012-05-15 2323 per_cpu_trap_init(true); 25517ed4e99b3be Huacai Chen 2018-11-10 2324 memblock_set_bottom_up(false); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2325 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2326 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2327 * Copy the generic exception handlers to their final destination. 92a76f6d8545efc Adam Buchbinder 2016-02-25 2328 * This will be overridden later as suitable for a particular ^1da177e4c3f415 Linus Torvalds 2005-04-16 2329 * configuration. ^1da177e4c3f415 Linus Torvalds 2005-04-16 2330 */ e01402b115cccb6 Ralf Baechle 2005-07-14 2331 set_handler(0x180, &except_vec3_generic, 0x80); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2332 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2333 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2334 * Setup default vectors ^1da177e4c3f415 Linus Torvalds 2005-04-16 2335 */ ^1da177e4c3f415 Linus Torvalds 2005-04-16 2336 for (i = 0; i <= 31; i++) ^1da177e4c3f415 Linus Torvalds 2005-04-16 2337 set_except_vector(i, handle_reserved); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2338 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2339 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2340 * Copy the EJTAG debug exception vector handler code to it's final ^1da177e4c3f415 Linus Torvalds 2005-04-16 2341 * destination. ^1da177e4c3f415 Linus Torvalds 2005-04-16 2342 */ e01402b115cccb6 Ralf Baechle 2005-07-14 2343 if (cpu_has_ejtag && board_ejtag_handler_setup) e01402b115cccb6 Ralf Baechle 2005-07-14 2344 board_ejtag_handler_setup(); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2345 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2346 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2347 * Only some CPUs have the watch exceptions. ^1da177e4c3f415 Linus Torvalds 2005-04-16 2348 */ ^1da177e4c3f415 Linus Torvalds 2005-04-16 2349 if (cpu_has_watch) 1b505defe051749 James Hogan 2015-12-16 2350 set_except_vector(EXCCODE_WATCH, handle_watch); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2351 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2352 /* e01402b115cccb6 Ralf Baechle 2005-07-14 2353 * Initialise interrupt handlers ^1da177e4c3f415 Linus Torvalds 2005-04-16 2354 */ e01402b115cccb6 Ralf Baechle 2005-07-14 2355 if (cpu_has_veic || cpu_has_vint) { e01402b115cccb6 Ralf Baechle 2005-07-14 2356 int nvec = cpu_has_veic ? 64 : 8; e01402b115cccb6 Ralf Baechle 2005-07-14 2357 for (i = 0; i < nvec; i++) e01402b115cccb6 Ralf Baechle 2005-07-14 2358 set_vi_handler(i, NULL); e01402b115cccb6 Ralf Baechle 2005-07-14 2359 } e01402b115cccb6 Ralf Baechle 2005-07-14 2360 else if (cpu_has_divec) e01402b115cccb6 Ralf Baechle 2005-07-14 2361 set_handler(0x200, &except_vec4, 0x8); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2362 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2363 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2364 * Some CPUs can enable/disable for cache parity detection, but does ^1da177e4c3f415 Linus Torvalds 2005-04-16 2365 * it different ways. ^1da177e4c3f415 Linus Torvalds 2005-04-16 2366 */ ^1da177e4c3f415 Linus Torvalds 2005-04-16 2367 parity_protection_init(); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2368 ^1da177e4c3f415 Linus Torvalds 2005-04-16 2369 /* ^1da177e4c3f415 Linus Torvalds 2005-04-16 2370 * The Data Bus Errors / Instruction Bus Errors are signaled ^1da177e4c3f415 Linus Torvalds 2005-04-16 2371 * by external hardware. Therefore these two exceptions ^1da177e4c3f415 Linus Torvalds 2005-04-16 2372 * may have board specific handlers. ^1da177e4c3f415 Linus Torvalds 2005-04-16 2373 */ ^1da177e4c3f415 Linus Torvalds 2005-04-16 2374 if (board_be_init) ^1da177e4c3f415 Linus Torvalds 2005-04-16 2375 board_be_init(); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2376 1b505defe051749 James Hogan 2015-12-16 2377 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 1b505defe051749 James Hogan 2015-12-16 2378 rollback_handle_int : handle_int); 1b505defe051749 James Hogan 2015-12-16 2379 set_except_vector(EXCCODE_MOD, handle_tlbm); 1b505defe051749 James Hogan 2015-12-16 2380 set_except_vector(EXCCODE_TLBL, handle_tlbl); 1b505defe051749 James Hogan 2015-12-16 2381 set_except_vector(EXCCODE_TLBS, handle_tlbs); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2382 1b505defe051749 James Hogan 2015-12-16 2383 set_except_vector(EXCCODE_ADEL, handle_adel); 1b505defe051749 James Hogan 2015-12-16 2384 set_except_vector(EXCCODE_ADES, handle_ades); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2385 1b505defe051749 James Hogan 2015-12-16 2386 set_except_vector(EXCCODE_IBE, handle_ibe); 1b505defe051749 James Hogan 2015-12-16 2387 set_except_vector(EXCCODE_DBE, handle_dbe); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2388 1b505defe051749 James Hogan 2015-12-16 2389 set_except_vector(EXCCODE_SYS, handle_sys); 1b505defe051749 James Hogan 2015-12-16 2390 set_except_vector(EXCCODE_BP, handle_bp); 5a34133167dce36 Huacai Chen 2017-03-16 2391 5a34133167dce36 Huacai Chen 2017-03-16 2392 if (rdhwr_noopt) 5a34133167dce36 Huacai Chen 2017-03-16 2393 set_except_vector(EXCCODE_RI, handle_ri); 5a34133167dce36 Huacai Chen 2017-03-16 2394 else { 5a34133167dce36 Huacai Chen 2017-03-16 2395 if (cpu_has_vtag_icache) 5a34133167dce36 Huacai Chen 2017-03-16 2396 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 268a2d60013049c Jiaxun Yang 2019-10-20 2397 else if (current_cpu_type() == CPU_LOONGSON64) 5a34133167dce36 Huacai Chen 2017-03-16 2398 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 5a34133167dce36 Huacai Chen 2017-03-16 2399 else 5a34133167dce36 Huacai Chen 2017-03-16 2400 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 5a34133167dce36 Huacai Chen 2017-03-16 2401 } 5a34133167dce36 Huacai Chen 2017-03-16 2402 1b505defe051749 James Hogan 2015-12-16 2403 set_except_vector(EXCCODE_CPU, handle_cpu); 1b505defe051749 James Hogan 2015-12-16 2404 set_except_vector(EXCCODE_OV, handle_ov); 1b505defe051749 James Hogan 2015-12-16 2405 set_except_vector(EXCCODE_TR, handle_tr); 1b505defe051749 James Hogan 2015-12-16 2406 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); ^1da177e4c3f415 Linus Torvalds 2005-04-16 2407 e01402b115cccb6 Ralf Baechle 2005-07-14 @2408 if (board_nmi_handler_setup) e01402b115cccb6 Ralf Baechle 2005-07-14 2409 board_nmi_handler_setup(); e01402b115cccb6 Ralf Baechle 2005-07-14 2410 e50c0a8fa60da9a Ralf Baechle 2005-05-31 2411 if (cpu_has_fpu && !cpu_has_nofpuex) 1b505defe051749 James Hogan 2015-12-16 @2412 set_except_vector(EXCCODE_FPE, handle_fpe); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2413 1b505defe051749 James Hogan 2015-12-16 2414 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 5890f70f15c52d0 Leonid Yegoshin 2014-07-15 2415 5890f70f15c52d0 Leonid Yegoshin 2014-07-15 2416 if (cpu_has_rixiex) { 1b505defe051749 James Hogan 2015-12-16 2417 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 1b505defe051749 James Hogan 2015-12-16 2418 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 5890f70f15c52d0 Leonid Yegoshin 2014-07-15 2419 } 5890f70f15c52d0 Leonid Yegoshin 2014-07-15 2420 1b505defe051749 James Hogan 2015-12-16 2421 set_except_vector(EXCCODE_MSADIS, handle_msa); 1b505defe051749 James Hogan 2015-12-16 2422 set_except_vector(EXCCODE_MDMX, handle_mdmx); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2423 e50c0a8fa60da9a Ralf Baechle 2005-05-31 2424 if (cpu_has_mcheck) 1b505defe051749 James Hogan 2015-12-16 2425 set_except_vector(EXCCODE_MCHECK, handle_mcheck); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2426 340ee4b98c0543b Ralf Baechle 2005-08-17 2427 if (cpu_has_mipsmt) 1b505defe051749 James Hogan 2015-12-16 2428 set_except_vector(EXCCODE_THREAD, handle_mt); 340ee4b98c0543b Ralf Baechle 2005-08-17 2429 1b505defe051749 James Hogan 2015-12-16 2430 set_except_vector(EXCCODE_DSPDIS, handle_dsp); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2431 fcbf1dfde3da728 David Daney 2012-05-15 2432 if (board_cache_error_setup) fcbf1dfde3da728 David Daney 2012-05-15 2433 board_cache_error_setup(); fcbf1dfde3da728 David Daney 2012-05-15 2434 e50c0a8fa60da9a Ralf Baechle 2005-05-31 2435 if (cpu_has_vce) e50c0a8fa60da9a Ralf Baechle 2005-05-31 2436 /* Special exception: R4[04]00 uses also the divec space. */ 2a0b24f56c2492b Steven J. Hill 2013-03-25 2437 set_handler(0x180, &except_vec3_r4000, 0x100); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2438 else if (cpu_has_4kex) 2a0b24f56c2492b Steven J. Hill 2013-03-25 2439 set_handler(0x180, &except_vec3_generic, 0x80); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2440 else 2a0b24f56c2492b Steven J. Hill 2013-03-25 2441 set_handler(0x080, &except_vec3_generic, 0x80); e50c0a8fa60da9a Ralf Baechle 2005-05-31 2442 783454e2bc7ce49 Paul Burton 2019-04-30 2443 local_flush_icache_range(ebase, ebase + vec_size); 0510617b85758b6 Thomas Bogendoerfer 2008-08-04 2444 0510617b85758b6 Thomas Bogendoerfer 2008-08-04 2445 sort_extable(__start___dbe_table, __stop___dbe_table); 69f3a7de1f1ec93 Ralf Baechle 2009-11-24 2446 4483b159168d3db Ralf Baechle 2010-08-05 2447 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ ^1da177e4c3f415 Linus Torvalds 2005-04-16 2448 } ae4ce45419f908c James Hogan 2014-03-04 2449 :::::: The code at line 2408 was first introduced by commit :::::: e01402b115cccb6357f956649487aca2c6f7fbba More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. :::::: TO: Ralf Baechle <[email protected]> :::::: CC: Ralf Baechle <[email protected]> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
