On Wed, Aug 26, 2020 at 03:14:07PM +0800, peng....@nxp.com wrote: > From: Peng Fan <peng....@nxp.com> > > According to RM, for peripheral clock slice, > "IP clock slices must be stopped to change the clock source.". > > So we must have CLK_SET_PARENT_GATE flag to avoid glitch. > > Signed-off-by: Peng Fan <peng....@nxp.com>
Applied, thanks.
