Reorder definition of variables in the code to have them sorted by length in order to make code easier to read.
Reviewed-by: Michał Mirosław <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> --- drivers/i2c/busses/i2c-tegra.c | 61 +++++++++++++--------------------- 1 file changed, 24 insertions(+), 37 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index f38e0f3fe367..5ecc9f7c9b78 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -290,13 +290,12 @@ struct tegra_i2c_dev { static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev); -static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, - unsigned long reg) +static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, u32 reg) { writel_relaxed(val, i2c_dev->base + reg); } -static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) +static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, u32 reg) { return readl_relaxed(i2c_dev->base + reg); } @@ -305,8 +304,7 @@ static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) * i2c_writel and i2c_readl will offset the register if necessary to talk * to the I2C block inside the DVC block */ -static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, - unsigned long reg) +static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, u32 reg) { if (i2c_dev->is_dvc) reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; @@ -315,8 +313,7 @@ static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, return reg; } -static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, - unsigned long reg) +static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, u32 reg) { writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); @@ -325,19 +322,19 @@ static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); } -static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) +static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, u32 reg) { return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); } static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, - unsigned long reg, int len) + u32 reg, int len) { writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, - unsigned long reg, int len) + u32 reg, int len) { readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } @@ -412,8 +409,8 @@ static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) { struct dma_chan *chan; - u32 *dma_buf; dma_addr_t dma_phys; + u32 *dma_buf; int err; if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) @@ -505,11 +502,11 @@ static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) { - u32 val; - int rx_fifo_avail; - u8 *buf = i2c_dev->msg_buf; size_t buf_remaining = i2c_dev->msg_buf_remaining; + u8 *buf = i2c_dev->msg_buf; int words_to_transfer; + int rx_fifo_avail; + u32 val; /* * Catch overflow due to message fully sent @@ -566,11 +563,11 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) { - u32 val; - int tx_fifo_avail; - u8 *buf = i2c_dev->msg_buf; size_t buf_remaining = i2c_dev->msg_buf_remaining; + u8 *buf = i2c_dev->msg_buf; int words_to_transfer; + int tx_fifo_avail; + u32 val; if (i2c_dev->hw->has_mst_fifo) { val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); @@ -754,12 +751,8 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { - u32 val; + u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; int err; - u32 clk_divisor, clk_multiplier; - u32 non_hs_mode; - u32 tsu_thd; - u8 tlow, thigh; err = reset_control_reset(i2c_dev->rst); WARN_ON_ONCE(err); @@ -872,9 +865,9 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) { - u32 status; const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; struct tegra_i2c_dev *i2c_dev = dev_id; + u32 status; status = i2c_readl(i2c_dev, I2C_INT_STATUS); @@ -977,12 +970,10 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) static int tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, size_t len) { - u32 val, reg; - u8 dma_burst; struct dma_slave_config slv_config = {0}; + u32 val, reg, dma_burst, reg_offset; struct dma_chan *chan; int ret; - unsigned long reg_offset; if (i2c_dev->hw->has_mst_fifo) reg = I2C_MST_FIFO_CONTROL; @@ -1108,9 +1099,8 @@ tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev, static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) { struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + u32 reg, time_left; int err; - unsigned long time_left; - u32 reg; reinit_completion(&i2c_dev->msg_complete); reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | @@ -1148,13 +1138,11 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *msg, enum msg_end_type end_state) { - u32 packet_header; - u32 int_mask; - unsigned long time_left; - size_t xfer_size; + unsigned long time_left, xfer_time = 100; + u32 packet_header, int_mask; u32 *buffer = NULL; - int err = 0; - u16 xfer_time = 100; + size_t xfer_size; + int err; err = tegra_i2c_flush_fifos(i2c_dev); if (err) @@ -1353,8 +1341,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); - int i; - int ret; + int i, ret; ret = pm_runtime_get_sync(i2c_dev->dev); if (ret < 0) { @@ -1408,8 +1395,8 @@ static u32 tegra_i2c_func(struct i2c_adapter *adap) static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { struct device_node *np = i2c_dev->dev->of_node; - int ret; bool multi_mode; + int ret; ret = of_property_read_u32(np, "clock-frequency", &i2c_dev->bus_clk_rate); -- 2.27.0
