On Mon, 07 Sep 2020, Xu Yilun wrote: > This patch implements the basic functions of the BMC chip for some Intel > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the > Intel MAX 10 CPLD. > > This BMC chip is connected to the FPGA by a SPI bus. To provide direct > register access from the FPGA, the "SPI slave to Avalon Master Bridge" > (spi-avmm) IP is integrated in the chip. It converts encoded streams of > bytes from the host to the internal register read/write on the Avalon > bus. So This driver uses the regmap-spi-avmm for register accessing. > > Signed-off-by: Xu Yilun <[email protected]> > Signed-off-by: Wu Hao <[email protected]> > Signed-off-by: Matthew Gerlach <[email protected]> > Signed-off-by: Russ Weight <[email protected]> > Reviewed-by: Tom Rix <[email protected]> > --- > v2: Split out the regmap-spi-avmm part. > Rename the file intel-m10-bmc-main.c to intel-m10-bmc.c, cause > there is only one source file left for this module now. > v3: Add the sub devices in mfd_cell. > Some minor fixes. > v4: No change. > v5: Changes the names of mfd_cell. > Use ATTRIBUTE_GROUPS() to simplify the code. > Use the generic 'ddata' for the instance of struct intel_m10bmc. > More comments to clarify the function check_m10bmc_version(). > Some minor fixes. > --- > .../ABI/testing/sysfs-driver-intel-m10-bmc | 15 ++ > drivers/mfd/Kconfig | 13 ++ > drivers/mfd/Makefile | 2 + > drivers/mfd/intel-m10-bmc.c | 162 > +++++++++++++++++++++ > include/linux/mfd/intel-m10-bmc.h | 56 +++++++ > 5 files changed, 248 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-m10-bmc > create mode 100644 drivers/mfd/intel-m10-bmc.c > create mode 100644 include/linux/mfd/intel-m10-bmc.h
Please see my replies for v4. -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
