On Fri, 2020-09-11 at 16:45 -0600, Rob Herring wrote:
> On Thu, Sep 10, 2020 at 11:45:34AM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> >
> > Signed-off-by: Jianjun Wang <jianjun.w...@mediatek.com>
> > Acked-by: Ryder Lee <ryder....@mediatek.com>
> > ---
> > .../bindings/pci/mediatek-pcie-gen3.yaml | 130 ++++++++++++++++++
> > 1 file changed, 130 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > new file mode 100644
> > index 000000000000..a2dfc0d15d2e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -0,0 +1,130 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Gen3 PCIe controller on MediaTek SoCs
> > +
> > +maintainers:
> > + - Jianjun Wang <jianjun.w...@mediatek.com>
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - const: mediatek,gen3-pcie
>
> Generic compatibles like this should only be a fallback string, not on
> its own.
>
> > + - const: mediatek,mt8192-pcie
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + bus-range:
> > + description: Range of bus numbers associated with this controller.
>
> Drop this. Standard property.
Thanks for your review, I will drop it in the next version.
>
> > +
> > + ranges:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + resets:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + reset-names:
> > + anyOf:
> > + - const: mac-rst
> > + - const: phy-rst
> > +
> > + clocks:
> > + maxItems: 5
> > +
> > + assigned-clocks:
> > + maxItems: 1
> > +
> > + assigned-clock-parents:
> > + maxItems: 1
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + '#interrupt-cells':
> > + const: 1
> > +
> > + interrupt-controller:
> > + description: Interrupt controller node for handling legacy PCI
> > interrupts.
> > + type: object
> > + properties:
> > + '#address-cells':
> > + const: 0
> > + '#interrupt-cells':
> > + const: 1
> > + interrupt-controller: true
> > +
> > + required:
> > + - '#address-cells'
> > + - '#interrupt-cells'
> > + - interrupt-controller
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - ranges
> > + - clocks
> > + - '#interrupt-cells'
> > + - interrupt-controller
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + bus {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie: pcie@11230000 {
> > + compatible = "mediatek,mt8192-pcie";
> > + device_type = "pci";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + reg = <0x00 0x11230000 0x00 0x4000>;
> > + reg-names = "pcie-mac";
> > + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00
> > 0x1000000>;
> > + clocks = <&infracfg 40>,
> > + <&infracfg 43>,
> > + <&infracfg 97>,
> > + <&infracfg 99>,
> > + <&infracfg 111>;
> > + assigned-clocks = <&topckgen 50>;
> > + assigned-clock-parents = <&topckgen 91>;
> > +
> > + phys = <&pciephy>;
> > + phy-names = "pcie-phy";
> > + resets = <&infracfg_rst 0>;
> > + reset-names = "phy-rst";
> > +
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &pcie_intc 0>,
> > + <0 0 0 2 &pcie_intc 1>,
> > + <0 0 0 3 &pcie_intc 2>,
> > + <0 0 0 4 &pcie_intc 3>;
> > + pcie_intc: interrupt-controller {
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > --
> > 2.25.1
