The feature of color zero pages isn't enabled on arm64, meaning all read-only (anonymous) VM areas are backed up by same zero page. It leads pressure to L1 (data) cache on reading data from them. This tries to enable color zero pages.
PATCH[1/2] decouples the zero PGD table from zero page PATCH[2/2] allocates the needed zero pages according to L1 cache size Changelog ========= v2: * Rebased to 5.9.rc6 (Gavin) * Retrieve cache topology from ACPI/DT (Will/Robin) Gavin Shan (2): arm64/mm: Introduce zero PGD table arm64/mm: Enable color zero pages arch/arm64/include/asm/cache.h | 3 ++ arch/arm64/include/asm/mmu_context.h | 6 +-- arch/arm64/include/asm/pgtable.h | 11 ++++- arch/arm64/kernel/cacheinfo.c | 67 ++++++++++++++++++++++++++++ arch/arm64/kernel/setup.c | 2 +- arch/arm64/kernel/vmlinux.lds.S | 4 ++ arch/arm64/mm/init.c | 37 +++++++++++++++ arch/arm64/mm/mmu.c | 7 --- arch/arm64/mm/proc.S | 2 +- drivers/base/cacheinfo.c | 3 +- include/linux/cacheinfo.h | 6 +++ 11 files changed, 132 insertions(+), 16 deletions(-) -- 2.23.0
