On Mon, Sep 28, 2020 at 04:30:46PM +0800, Lai Jiangshan wrote:
> From: Lai Jiangshan <la...@linux.alibaba.com>
>
> When shadowpaping is enabled, guest should not be allowed
> to toggle X86_CR4_LA57. And X86_CR4_LA57 is a rarely changed
> bit, so we can just intercept all the attempts to toggle it
> no matter shadowpaping is in used or not.
>
> Fixes: fd8cb433734ee ("KVM: MMU: Expose the LA57 feature to VM.")
> Cc: Sean Christopherson <sean.j.christopher...@intel.com>
> Cc: Yu Zhang <yu.c.zh...@linux.intel.com>
> Cc: Paolo Bonzini <pbonz...@redhat.com>
> Signed-off-by: Lai Jiangshan <la...@linux.alibaba.com>
> ---
> No test to toggle X86_CR4_LA57 in guest since I can't access to
> any CPU supports it. Maybe it is not a real problem.
LA57 doesn't need to be intercepted. It can't be toggled in 64-bit mode
(causes a #GP), and it's ignored in 32-bit mode. That means LA57 can only
take effect when 64-bit mode is enabled, at which time KVM will update its
MMU context accordingly.
> arch/x86/kvm/kvm_cache_regs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h
> index cfe83d4ae625..ca0781b41df9 100644
> --- a/arch/x86/kvm/kvm_cache_regs.h
> +++ b/arch/x86/kvm/kvm_cache_regs.h
> @@ -7,7 +7,7 @@
> #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS
> #define KVM_POSSIBLE_CR4_GUEST_BITS \
> (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
> - | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_PGE | X86_CR4_TSD)
> + | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD)
>
> #define BUILD_KVM_GPR_ACCESSORS(lname, uname)
> \
> static __always_inline unsigned long kvm_##lname##_read(struct kvm_vcpu
> *vcpu)\
> --
> 2.19.1.6.gb485710b
>
