On 2020/9/29 3:16, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:24PM +0800, Zhen Lei wrote:
>> Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
>> controller binding to DT schema format using json-schema.
>>
>> Signed-off-by: Zhen Lei <thunder.leiz...@huawei.com>
>> ---
>> .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------
>> .../arm/hisilicon/hisilicon-low-pin-count.yaml | 61
>> ++++++++++++++++++++++
>> 2 files changed, 61 insertions(+), 33 deletions(-)
>> delete mode 100644
>> Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> create mode 100644
>> Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>>
>> b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> deleted file mode 100644
>> index 10bd35f9207f2ee..000000000000000
>> ---
>> a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> +++ /dev/null
>> @@ -1,33 +0,0 @@
>> -Hisilicon Hip06 Low Pin Count device
>> - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
>> - provides I/O access to some legacy ISA devices.
>> - Hip06 is based on arm64 architecture where there is no I/O space. So, the
>> - I/O ports here are not CPU addresses, and there is no 'ranges' property in
>> - LPC device node.
>> -
>> -Required properties:
>> -- compatible: value should be as follows:
>> - (a) "hisilicon,hip06-lpc"
>> - (b) "hisilicon,hip07-lpc"
>> -- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
>> -- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
>> -- reg: base memory range where the LPC register set is mapped.
>> -
>> -Note:
>> - The node name before '@' must be "isa" to represent the binding stick to
>> the
>> - ISA/EISA binding specification.
>> -
>> -Example:
>> -
>> -isa@a01b0000 {
>> - compatible = "hisilicon,hip06-lpc";
>> - #address-cells = <2>;
>> - #size-cells = <1>;
>> - reg = <0x0 0xa01b0000 0x0 0x1000>;
>> -
>> - ipmi0: bt@e4 {
>> - compatible = "ipmi-bt";
>> - device_type = "ipmi";
>> - reg = <0x01 0xe4 0x04>;
>> - };
>> -};
>> diff --git
>> a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>>
>> b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>> new file mode 100644
>> index 000000000000000..83ca10adce71b62
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>> @@ -0,0 +1,61 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>> http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon Hip06 Low Pin Count device
>> +
>> +maintainers:
>> + - Wei Xu <xuw...@hisilicon.com>
>> +
>> +description: |
>> + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
>> + provides I/O access to some legacy ISA devices.
>> + Hip06 is based on arm64 architecture where there is no I/O space. So, the
>> + I/O ports here are not CPU addresses, and there is no 'ranges' property in
>> + LPC device node.
>> +
>> +properties:
>> + $nodename:
>> + pattern: '^isa@[0-9a-f]+$'
>> + description: |
>> + The node name before '@' must be "isa" to represent the binding stick
>> + to the ISA/EISA binding specification.
>> +
>> + compatible:
>> + enum:
>> + - hisilicon,hip06-lpc
>> + - hisilicon,hip07-lpc
>> +
>> + reg:
>> + description: base memory range where the LPC register set is mapped.
>
> Drop description.
OK
>
>> + maxItems: 1
>> +
>> + '#address-cells':
>> + description: must be 2 which stick to the ISA/EISA binding doc.
>
> Drop.
OK
>
>> + const: 2
>> +
>> + '#size-cells':
>> + description: must be 1 which stick to the ISA/EISA binding doc.
>
> Drop.
OK
>
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>
> additionalProperties:
> type: object
OK, I will add it.
>
>> +
>> +examples:
>> + - |
>> + isa@a01b0000 {
>> + compatible = "hisilicon,hip06-lpc";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + reg = <0xa01b0000 0x1000>;
>> +
>> + ipmi0: bt@e4 {
>> + compatible = "ipmi-bt";
>> + device_type = "ipmi";
>> + reg = <0x01 0xe4 0x04>;
>> + };
>> + };
>> +...
>> --
>> 1.8.3
>>
>>
>
> .
>
