From: Jonathan Bakker <xc-rac...@live.ca>
[ Upstream commit 05942b8c36c7eb5d3fc5e375d4b0d0c49562e85d ]
The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.
This manifested in issues with the DWC2 driver since commit fe369e1826b3
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.
Signed-off-by: Jonathan Bakker <xc-rac...@live.ca>
Link:
https://lore.kernel.org/r/bn6pr04mb06605d52502816e500683553a3...@bn6pr04mb0660.namprd04.prod.outlook.com
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
drivers/phy/samsung/phy-s5pv210-usb2.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/samsung/phy-s5pv210-usb2.c
b/drivers/phy/samsung/phy-s5pv210-usb2.c
index 56a5083fe6f94..32be62e498047 100644
--- a/drivers/phy/samsung/phy-s5pv210-usb2.c
+++ b/drivers/phy/samsung/phy-s5pv210-usb2.c
@@ -139,6 +139,10 @@ static void s5pv210_phy_pwr(struct
samsung_usb2_phy_instance *inst, bool on)
udelay(10);
rst &= ~rstbits;
writel(rst, drv->reg_phy + S5PV210_UPHYRST);
+ /* The following delay is necessary for the reset sequence to be
+ * completed
+ */
+ udelay(80);
} else {
pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
pwr |= phypwr;
--
2.25.1
