Add feature enumeration to identify a hybrid part: one in which CPUs with more than one type of micro-architecture exists in the same package.
Cc: Andi Kleen <[email protected]> Cc: Kan Liang <[email protected]> Cc: Len Brown <[email protected]> Cc: "Peter Zijlstra (Intel)" <[email protected]> Cc: "Rafael J. Wysocki" <[email protected]> Cc: "Ravi V. Shankar" <[email protected]> Cc: Srinivas Pandruvada <[email protected]> Cc: [email protected] Reviewed-by: Tony Luck <[email protected]> Signed-off-by: Ricardo Neri <[email protected]> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dad350d42ecf..26ecc0f2a6fd 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -371,6 +371,7 @@ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ +#define X86_FEATURE_HYBRID_CPU (18*32+15) /* This part has CPUs of more than one type */ #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ -- 2.17.1
