Hi Bjorn, This patch has been acked and unchanged for weeks. Is it possible to get this pulled into next? We have SIOV and CXL related work that is using these definitions. Thanks.
David On Fri, 2020-10-02 at 18:31 -0700, David E. Box wrote: > Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and > defines > for the header offsets. Defined in PCIe r5.0, sec 7.9.6. > > Signed-off-by: David E. Box <david.e....@linux.intel.com> > Acked-by: Bjorn Helgaas <bhelg...@google.com> > Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h > b/include/uapi/linux/pci_regs.h > index f9701410d3b5..beafeee39e44 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -720,6 +720,7 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port > Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement > */ > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific > */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer > 16.0 GT/s */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT > @@ -1062,6 +1063,10 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* > LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register > */ > > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > +#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor- > Specific Header1 */ > +#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor- > Specific Header2 */ > + > /* Data Link Feature */ > #define PCI_DLF_CAP 0x04 /* Capabilities Register */ > #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link > Feature Exchange Enable */
