On Mon, 12 Oct 2020, Rafael J. Wysocki wrote: > > @@ -20,7 +20,11 @@ > > * All CPUs have same idle states as boot CPU > > * > > * Chipset BM_STS (bus master status) bit is a NOP > > - * for preventing entry into deep C-stats > > + * for preventing entry into deep C-states > > + * > > + * CPU will flush caches as needed when entering a C-state via MWAIT > > I would rephrase this to mention that the above actually is an assumption.
This comment block is by itself a list of assumptions. It begins with heading "Design Assumptions" and then lists two assumptions. This patch adds a third one. With that clarified, do you still need me to change this hunk? > > > + * (in contrast to entering ACPI C3, where acpi_idle driver is > > And mentioning acpi_idle here is not needed; it would be sufficient to > say something like "in which case the WBINVD instruction needs to be > executed to flush the caches". I see, thanks, I will change this for v2 once the above is cleared up. Thanks. Alexander
