These do not all strictly belong to the g1 core and even the majority
of previously documented bits were not used (yet) by the driver irq
handlers, but it's still very useful to have an overview of all IRQs,
especially since starting with core versions vc8000 and later the irq
bits previously used by G1 and G2 have been merged at the same address.
Signed-off-by: Adrian Ratiu <adrian.ra...@collabora.com>
---
drivers/staging/media/hantro/hantro_g1_regs.h | 39 +++++++++++++------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h
b/drivers/staging/media/hantro/hantro_g1_regs.h
index c1756e3d5391..80ff297f6f68 100644
--- a/drivers/staging/media/hantro/hantro_g1_regs.h
+++ b/drivers/staging/media/hantro/hantro_g1_regs.h
@@ -13,17 +13,34 @@
/* Decoder registers. */
#define G1_REG_INTERRUPT 0x004
-#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24)
-#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18)
-#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
-#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16)
-#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15)
-#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
-#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13)
-#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12)
-#define G1_REG_INTERRUPT_DEC_IRQ BIT(8)
-#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4)
-#define G1_REG_INTERRUPT_DEC_E BIT(0)
+/* Interrupt bits. Some are present in:
+ * - all core versions (">= g1")
+ * - g1, missing in g2, but added back starting with vc8000d ("not in g2")
+ * - vc8000d and later (">= vc8000d")
+ */
+#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) /* not in g2 */
+#define G1_REG_INTERRUPT_DEC_TILE_INT BIT(23) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_LINE_CNT_INT BIT(22) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_EXT_TIMEOUT_INT BIT(21) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_NO_SLICE_INT BIT(20) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_LAST_SLICE_INT BIT(19) /* >=
vc8000d */
+#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) /* not in g2 */
+#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) /* not in g2 */
+#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_ABORT_INT BIT(11) /* >= g2 */
+#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_TILE_INT_E BIT(7) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_SELF_RESET_DIS BIT(6) /* >=
vc8000d */
+#define G1_REG_INTERRUPT_DEC_ABORT_E BIT(5) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) /* >= g1 */
+#define G1_REG_INTERRUPT_DEC_TIMEOUT_SOURCE BIT(3) /* >=
vc8000d */
+#define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */
+#define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >=
vc8000d */
+#define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */
#define G1_REG_CONFIG 0x008
#define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
#define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23)
--
2.28.0
