Stephen Boyd Tue, 13 Oct 2020 19:49:01 -0700
Quoting Qiang Zhao (2020-09-15 20:03:10) > From: Zhao Qiang <qiang.z...@nxp.com> > > On LS2088A, Watchdog need clk divided by 32, > so modify MAX_PLL_DIV to 32 > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > ---
Applied to clk-next