Quoting Paul Cercueil (2020-09-02 18:50:46) > CLK_SET_RATE_GATE means that the clock must be gated when being > reclocked. This is not the case for the PLLs in Ingenic SoCs. > > Signed-off-by: Paul Cercueil <p...@crapouillou.net> > ---
Applied to clk-next