Add MT8192 imp i2c wrapper e clock provider Signed-off-by: Weiyi Lu <weiyi...@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c | 59 ++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index a0eb76d..5c298ee 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -497,6 +497,12 @@ config COMMON_CLK_MT8192_IMP_IIC_WRAP_C help This driver supports MediaTek MT8192 imp_iic_wrap_c clocks. +config COMMON_CLK_MT8192_IMP_IIC_WRAP_E + bool "Clock driver for MediaTek MT8192 imp_iic_wrap_e" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 imp_iic_wrap_e clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 8aac821..3aae75e 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -70,5 +70,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWC) += clk-mt8192-cam_rawc.o obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS2) += clk-mt8192-img2.o obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_C) += clk-mt8192-imp_iic_wrap_c.o +obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_E) += clk-mt8192-imp_iic_wrap_e.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c new file mode 100644 index 0000000..84043a5c --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi...@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs imp_iic_wrap_e_cg_regs = { + .set_ofs = 0xe08, + .clr_ofs = 0xe04, + .sta_ofs = 0xe00, +}; + +#define GATE_IMP_IIC_WRAP_E(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_e_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate imp_iic_wrap_e_clks[] = { + GATE_IMP_IIC_WRAP_E(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0), +}; + +static int clk_mt8192_imp_iic_wrap_e_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_E_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, imp_iic_wrap_e_clks, ARRAY_SIZE(imp_iic_wrap_e_clks), + clk_data); + if (r) + return r; + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_e[] = { + { .compatible = "mediatek,mt8192-imp_iic_wrap_e", }, + {} +}; + +static struct platform_driver clk_mt8192_imp_iic_wrap_e_drv = { + .probe = clk_mt8192_imp_iic_wrap_e_probe, + .driver = { + .name = "clk-mt8192-imp_iic_wrap_e", + .of_match_table = of_match_clk_mt8192_imp_iic_wrap_e, + }, +}; + +builtin_platform_driver(clk_mt8192_imp_iic_wrap_e_drv); -- 1.8.1.1.dirty