Dick Johnson wrote:
You can't just touch a scope-probe to the PCI clock pin and clip the scope-probe grounding lead to a convenient "ground" to make these measurements! You need a special fixture that will make a low-inductance connection to the PCI bus in the same manner as the interface chip.
(This is waaay over my head.) Why do you think the two plots (at least the second one) were not obtained as you describe? Why would the system manufacturer botch the measurements when I asked them to show me evidence that their system was compliant?
A scope probe will allow you to see if there is a clock signal. That's all. You can't determine its quality. A 4-inch ground lead on the scope probe will result in 10-20% overshoot and undershoot being observed.
I don't understand this 10-20% figure. (0V + 10-20% is still 0V.) AFAIU, the nominal peak-to-peak voltage is 3.3V. The observed peak-to-peak voltage is 6.08V (3.3V + 84%). Regards. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
