Hi guys, Sorry for the issues introduced and reported by 0day testing, and for taking a bit longer to sort them out. I hope I've done this in this version.
The only ones I've not solved are the unused function warnings: arch/arm64/kernel/topology.c:140:1: warning: unused function 'store_corecnt' [-Wunused-function] COUNTER_READ_STORE(corecnt, 0); [..] arch/arm64/kernel/topology.c:141:1: warning: unused function 'store_constcnt' [-Wunused-function] COUNTER_READ_STORE(constcnt, 0); After the 3 patches are applied, these only happen for !CONFIG_ACPI_CPPC_LIB. Therefore I thought fixing these might not be worth the ifdef guarding required to fix it. Let me know if you think otherwise. v2 -> v3: - v2 can be found at [3] - Sorted out part of the issues flagged by 0day testing in patches 1/3 and 3/3. - This version is based on v5.10-rc2. RESEND v2: - Rebased and retested on v5.10-rc1. v1 -> v2: - v1 can be found at [2] - The previous patch 1/4 was removed and a get_cpu_with_amu_feat() function was introduced instead, in 3/3, as suggested by Catalin. Given that most checks for the presence of AMUs is done at CPU level, followed by other validation, this implementation works better than the one initially introduced in v1/->patch 1/4. - Fixed warning reported by 0-day kernel test robot. - All build tests and FVP tests at [2] were re-run for this version. - This version is based on linux-next/20201001. [1] https://documentation-service.arm.com/static/5f106ad60daa596235e80081 [2] https://lore.kernel.org/lkml/[email protected]/ [3] https://lore.kernel.org/linux-arm-kernel/[email protected]/ Thank you, Ionela. Ionela Voinescu (3): arm64: wrap and generalise counter read functions arm64: split counter validation function arm64: implement CPPC FFH support using AMUs arch/arm64/include/asm/cpufeature.h | 8 ++ arch/arm64/include/asm/topology.h | 4 +- arch/arm64/kernel/cpufeature.c | 13 ++- arch/arm64/kernel/topology.c | 132 ++++++++++++++++++++++------ 4 files changed, 124 insertions(+), 33 deletions(-) -- 2.17.1
