Hi Shiju, On 05/11/2020 17:42, Shiju Jose wrote: > For the firmware-first error handling on ARM64 hardware platforms, > CPU cache corrected error count is not recorded. > Create an CPU EDAC device and device blocks for the CPU caches > for this purpose. The EDAC device blocks are created based on the > CPU caches information represented in the ACPI PPTT.
Using the PPTT won't work on x86 systems. Can we use the core-code's common data to learn about caches: struct cpu_cacheinfo and struct cacheinfo ? Thanks, James
