On Mon, Nov 09, 2020 at 02:41:48PM -0600, Tom Lendacky wrote:
> On 11/9/20 11:35 AM, Arvind Sankar wrote:
> > The PAT bit is in different locations for 4k and 2M/1G page table
> > entries.
> >
> > Add a definition for _PAGE_LARGE_CACHE_MASK to represent the three
> > caching bits (PWT, PCD, PAT), similar to _PAGE_CACHE_MASK for 4k pages,
> > and use it in the definition of PMD_FLAGS_DEC_WP to get the correct PAT
> > index for write-protected pages.
> >
> > Remove a duplication definition of _PAGE_PAT_LARGE.
> >
> > Signed-off-by: Arvind Sankar <nived...@alum.mit.edu>
>
> Fixes: tag?
It's been broken since it was added in
6ebcb060713f ("x86/mm: Add support to encrypt the kernel in-place")
but the code has been restructured since then. I think it should be
backportable to 4.19.x if you want, except for that "duplication
definition"[sic] I removed, which was only added in v5.6. Do I need to
split that out into a separate patch?
>
> Tested-by: Tom Lendacky <thomas.lenda...@amd.com>
>
> > ---
> > arch/x86/include/asm/pgtable_types.h | 3 +--
> > arch/x86/mm/mem_encrypt_identity.c | 4 ++--
> > 2 files changed, 3 insertions(+), 4 deletions(-)
> >
