From: Michael Srba <[email protected]> Fix regulators on rt5033 by converting some values to bitmasks which were errorneously not defined as such in the header file.
Cc: Beomho Seo <[email protected]> Fixes: 0b271258544b ("mfd: rt5033: Add Richtek RT5033 driver core.") Signed-off-by: Michael Srba <[email protected]> --- Tested on Samsung Galaxy A3 (sm-a3ulte). Other areas (e.g "RT5033 use internal timer need to set time") still look suspicious, but without access to a datasheet it's unfortunately hard to evaluate. Moreover, these values are not currently utilized so it's not clear what format would be expected. (it's however hard to argue for the removal of said values, since with the datasheet not being publicly available, this file may be the best documentation of them) --- include/linux/mfd/rt5033-private.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h index 3e1be588e029..964e656272ce 100644 --- a/include/linux/mfd/rt5033-private.h +++ b/include/linux/mfd/rt5033-private.h @@ -91,14 +91,14 @@ enum rt5033_reg { #define RT5033_RT_HZ_MASK 0x01 /* RT5033 control register */ -#define RT5033_CTRL_FCCM_BUCK_MASK 0x00 -#define RT5033_CTRL_BUCKOMS_MASK 0x01 -#define RT5033_CTRL_LDOOMS_MASK 0x02 -#define RT5033_CTRL_SLDOOMS_MASK 0x03 -#define RT5033_CTRL_EN_BUCK_MASK 0x04 -#define RT5033_CTRL_EN_LDO_MASK 0x05 -#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06 -#define RT5033_CTRL_LDO_SLEEP_MASK 0x07 +#define RT5033_CTRL_FCCM_BUCK_MASK BIT(0) +#define RT5033_CTRL_BUCKOMS_MASK BIT(1) +#define RT5033_CTRL_LDOOMS_MASK BIT(2) +#define RT5033_CTRL_SLDOOMS_MASK BIT(3) +#define RT5033_CTRL_EN_BUCK_MASK BIT(4) +#define RT5033_CTRL_EN_LDO_MASK BIT(5) +#define RT5033_CTRL_EN_SAFE_LDO_MASK BIT(6) +#define RT5033_CTRL_LDO_SLEEP_MASK BIT(7) /* RT5033 BUCK control register */ #define RT5033_BUCK_CTRL_MASK 0x1f @@ -247,11 +247,11 @@ enum rt5033_fuel_reg { #define RT5033_FUEL_BAT_PRESENT 0x02 /* RT5033 PMIC interrupts */ -#define RT5033_PMIC_IRQ_BUCKOCP 2 -#define RT5033_PMIC_IRQ_BUCKLV 3 -#define RT5033_PMIC_IRQ_SAFELDOLV 4 -#define RT5033_PMIC_IRQ_LDOLV 5 -#define RT5033_PMIC_IRQ_OT 6 -#define RT5033_PMIC_IRQ_VDDA_UV 7 +#define RT5033_PMIC_IRQ_BUCKOCP BIT(2) +#define RT5033_PMIC_IRQ_BUCKLV BIT(3) +#define RT5033_PMIC_IRQ_SAFELDOLV BIT(4) +#define RT5033_PMIC_IRQ_LDOLV BIT(5) +#define RT5033_PMIC_IRQ_OT BIT(6) +#define RT5033_PMIC_IRQ_VDDA_UV BIT(7) #endif /* __RT5033_PRIVATE_H__ */ -- 2.28.0
