On Mon, Nov 09, 2020 at 01:01:34PM +0000, Srinivas Kandagatla wrote:
> Add device tree binding Documentation details for Qualcomm SM8250
> LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandaga...@linaro.org>
> ---
> .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++++++++++++++++++
> 1 file changed, 129 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
> b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
> new file mode 100644
> index 000000000000..562520f41a33
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
> + Low Power Island (LPI) TLMM block
> +
> +maintainers:
> + - Srinivas Kandagatla <srinivas.kandaga...@linaro.org>
> +
> +description: |
> + This binding describes the Top Level Mode Multiplexer block found in the
> + LPASS LPI IP on most Qualcomm SoCs
> +
> +properties:
> + compatible:
> + const: qcom,sm8250-lpass-lpi-pinctrl
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + clocks:
> + items:
> + - description: LPASS Core voting clock
> + - description: LPASS Audio voting clock
> +
> + clock-names:
> + items:
> + - const: core
> + - const: audio
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + description: Specifying the pin number and flags, as defined in
> + include/dt-bindings/gpio/gpio.h
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> + '-pins$':
> + if:
> + type: object
> + then:
The hacky part was also the if/then. You can drop that (and keep 'type:
object').
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9])$"
> + minItems: 1
> + maxItems: 14
> +
> + function:
> + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
> + swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
> + swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
> + dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
> + i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
> + i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
> + i2s2_data1 ]
> + description:
> + Specify the alternative function to be configured for the
> specified
> + pins.
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> + default: 2
> + description:
> + Selects the drive strength for the specified pins, in mA.
> +
> + slew-rate:
> + enum: [0, 1, 2, 3]
> + default: 0
> + description: |
> + 0: No adjustments
> + 1: Higher Slew rate (faster edges)
> + 2: Lower Slew rate (slower edges)
> + 3: Reserved (No adjustments)
> +
> + bias-pull-down: true
> +
> + bias-pull-up: true
> +
> + bias-disable: true
> +
> + output-high: true
> +
> + output-low: true
> +
> + required:
> + - pins
> + - function
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/sound/qcom,q6afe.h>
> + lpi_tlmm: pinctrl@33c0000 {
> + compatible = "qcom,sm8250-lpass-lpi-pinctrl";
> + reg = <0x33c0000 0x20000>,
> + <0x355a000 0x1000>;
> + clocks = <&q6afecc LPASS_HW_MACRO_VOTE
> LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6afecc LPASS_HW_DCODEC_VOTE
> LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + clock-names = "core", "audio";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&lpi_tlmm 0 0 14>;
> + };
> --
> 2.21.0
>
