Michael, Stephen: Could you take this clk patch?
On Friday 06 November 2020 11:51:18 Marek Behún wrote: > Also, this is how A3720 WTMI code and ATF determines XTAL clock rate. > No reason for kernel to do it differently. > > Reviewed-by: Marek Behún <[email protected]> > > On Fri, 6 Nov 2020 11:00:39 +0100 > Pali Rohár <[email protected]> wrote: > > > From: Terry Zhou <[email protected]> > > > > There is an error in the current code that the XTAL MODE > > pin was set to NB MPP1_31 which should be NB MPP1_9. > > The latch register of NB MPP1_9 has different offset of 0x8. > > > > Signed-off-by: Terry Zhou <[email protected]> > > [pali: Fix pin name in commit message] > > Signed-off-by: Pali Rohár <[email protected]> > > Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC") > > Cc: [email protected] > > > > --- > > This patch is present in Marvell SDK and also in Marvell's kernel fork: > > https://github.com/MarvellEmbeddedProcessors/linux-marvell/commit/80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 > > > > Konstantin Porotchkin wrote on Github that Gregory Clement was notified > > about this patch, but as this patch is still not in mainline kernel I'm > > sending it again for review. > > > > In original commit message (only in commit message, not code) was > > specified MPP9 pin on South Bridge, but correct is North Bridge. > > --- > > drivers/clk/mvebu/armada-37xx-xtal.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c > > b/drivers/clk/mvebu/armada-37xx-xtal.c > > index e9e306d4e9af..41271351cf1f 100644 > > --- a/drivers/clk/mvebu/armada-37xx-xtal.c > > +++ b/drivers/clk/mvebu/armada-37xx-xtal.c > > @@ -13,8 +13,8 @@ > > #include <linux/platform_device.h> > > #include <linux/regmap.h> > > > > -#define NB_GPIO1_LATCH 0xC > > -#define XTAL_MODE BIT(31) > > +#define NB_GPIO1_LATCH 0x8 > > +#define XTAL_MODE BIT(9) > > > > static int armada_3700_xtal_clock_probe(struct platform_device *pdev) > > { >
