Hi, These patches provide generic infrastructure to determine TLB page size from page table entries alone. Perf will use this (for either data or code address) to aid in profiling TLB issues.
While most architectures only have page table aligned large pages, some (notably ARM64, Sparc64 and Power) provide non page table aligned large pages and need to provide their own implementation of these functions. I've provided (completely untested) implementations for ARM64 and Sparc64, but failed to penetrate the _many_ Power MMUs. I'm hoping Nick or Aneesh can help me out there.
