From: Kai Huang <[email protected]> Two new MSRs IA32_SEAMRR_PHYS_BASE and IA32_SEAMRR_PHYS_MASK are added in SPR for TDX. Add macro definition for both of them.
Signed-off-by: Kai Huang <[email protected]> --- arch/x86/include/asm/msr-index.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index aad12236b33c..f42da6b11b42 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -924,4 +924,12 @@ #define MSR_VM_IGNNE 0xc0010115 #define MSR_VM_HSAVE_PA 0xc0010117 +/* Intel SEAMRR */ +#define MSR_IA32_SEAMRR_PHYS_BASE 0x00001400 +#define MSR_IA32_SEAMRR_PHYS_MASK 0x00001401 + +#define MSR_IA32_SEAMRR_PHYS_BASE_CONFIGURED (1ULL << 3) +#define MSR_IA32_SEAMRR_PHYS_MASK_ENABLED (1ULL << 11) +#define MSR_IA32_SEAMRR_PHYS_MASK_LOCKED (1ULL << 10) + #endif /* _ASM_X86_MSR_INDEX_H */ -- 2.17.1
